Data transfer control apparatus, data transfer control system and data transfer control method

• US 6,513,078 B1
• Filed: 10/28/1998
• Issued: 01/28/2003
• Est. Priority Date: 11/19/1997
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kanoh, Toshiyuki, Kaganoi, Teruo
• Primary Examiner(s): Dharia, Rupal
• Application Number:
  US09/181,167
• Time in Patent Office: 1,553 Days
• Field of Search: 710/100-105, 710/107-117
• US Class Current: 710/104
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

Data transfer mode between a plurality of circuit mod modules connected to a data bus is dynamically switched between a time division, space-division multiplexing and so forth for improving data transfer efficiency. For example, the data bus of 4n bit width is used as two data bus of 2n bit width in certain period (transfer mode “b”), as one data bus of 4n bit width in a certain period (transfer mode “a”), and further as four data bus of n bit width in a further certain period (transfer mode “c”). A command of switching of the transfer mode is performed by a transfer control circuit common to respective circuit modules. In response to command of the transfer mode, switching of the bit width of data and switching of the bus connecting condition are performed by the bus adapter circuit.

Claims

1. A data transfer control apparatus for controlling data transfer between a plurality of circuit modules through a data bus comprising a data transfer controller for controlling a data transfer bit width of said data bus and a plurality of circuit module interfaces for performing transmission and reception of data between said circuit modules and said data bus;

wherein each interface includes a switch for switching control of said data transfer bit width of transmission and reception data depending upon a transfer mode of said data transfer controller.

2. A data transfer control apparatus as set forth in claim 1, wherein said data transfer controller performs control of said data transfer bit width by reading out information of a predetermined scheduling table per a predetermined period and according to the read out information.

3. A data transfer control apparatus as set forth in claim 2, wherein said data transfer controller comprises a counter counting a given period of clock pulses and a reader for reading out information of said scheduling table sequentially per said predetermined period.

4. A data transfer control apparatus as set forth in claim 1, wherein said data transfer controller performs control of said data transfer bit width depending upon a demand from said circuit module.

5. A data transfer control apparatus as set forth in claim 1, wherein said data transfer controller performs control of said data transfer bit width depending upon a convergence condition of said data bus.

6. A data transfer control apparatus as set forth in claim 1, wherein said data bus has a bit width of N which is an integer greater than or equal to two, said data transfer controller performs control of said data transfer bit width by switching control between a transfer mode performing data transfer of N bit width and a transfer mode performing data transfer of a bit width corresponding to a quotient derived by dividing N with at least one divisor which is other than one.

7. A data transfer control system performing data transfer between a plurality of circuit modules through a data bus having a predetermined bit width, comprising a bus bit width controller for controlling a data transfer bit width of said data bus and a plurality of circuit module interfaces for performing transmission and reception of data between said circuit modules and said data bus;

wherein each interface includes a switch for switching control of said data transfer bit width of transmission and reception data depending upon a transfer mode of said bus bit width controller.

8. A data transfer control system as set forth in claim 7, wherein said bus bit width controller performs control of said data transfer bit width by reading out information of a predetermined scheduling table per a predetermined period and according to the read out information.

9. A data transfer control system as set forth in claim 7, wherein said bus bit width controller performs control of said data transfer bit width depending upon a demand from said circuit module.

10. A data transfer control system as set forth in claim 7, wherein said bus bit width controller performs control of said data transfer bit width depending upon a convergence condition of said data bus.

11. A data transfer control system as set forth in claim 7, wherein said data bus has a bit width of N which is an integer greater than or equal to two, said bus bit width controller performs control of said data transfer bit width by switching control between a transfer mode performing data transfer of N bit width and a transfer mode performing data transfer of a bit width corresponding to a quotient derived by dividing N with at least one divisor which is other than one.

12. A data transfer system comprising:

a plurality of circuit modules;

a data bus having N bit width where N is an integer greater than or equal to two for transferring data between said circuit modules;

an interface for performing transmission and reception of data between said circuit modules and said data bus;

a data transfer controller for performing control of data transfer on said data bus between said circuit modules,

said data transfer controller comprising a first switch for switching between a transfer mode performing data transfer with said N bit width and a data transfer with a bit width of a quotient derived by dividing said integer N by at least one divisor which is other than one;

each of said interfaces comprising a second switch for switching control of a data bit width of transmission and reception data of said circuit modules depending upon the transfer mode of said first switch of said data transfer controller.

13. A data transfer system as set forth in claim 12, wherein said first switch selectively commands said transfer mode at a predetermined period.

14. A data transfer system as set forth in claim 12, wherein said first switch comprises a scheduling table for setting said transfer modes and a reader for sequentially reading out the content of said scheduling table at a predetermined period.

15. A data transfer system as set forth in claim 14, wherein said reader includes a counter for counting a timing pulse of a constant period, and the content of said scheduling table is read out according to the content of a count.

16. A data transfer system as set forth in claim 12, wherein said first switch determines the transfer mode in response to a transfer demand from each interface to command each of said interfaces.

17. A data transfer system as set forth in claim 12, wherein each interface comprises an address for adding address information for a transmission data and an address extractor for extracting said address information from a reception data, said reception data is obtained only when said extracted address is that of its own system.

18. A data transfer method controlling data transfer between a plurality of circuit modules through a data bus and a plurality of circuit module interfaces for performing transmission and reception of data between said circuit modules and said data bus, wherein each interface includes a switch for switching control of a data transfer bit width of transmission and reception data depending upon a transfer mode of a data transfer controller, comprising the step of controlling a data transfer bit width of said data bus.

19. A data transfer method as set forth in claim 18, which further comprises the steps of reading information of predetermined scheduling table and varying said data transfer bit width according to the read out information.

20. A data transfer method as set forth in claim 18, which comprises the step of varying said data transfer bit width according to command information in response to information commanding a change in data transfer bit width to accommodate a data transfer from one or more of said plurality of circuit modules.

21. A data transfer method as set forth in claim 18, which comprises the steps of detecting a convergence condition of said data bus and varying said data transfer bit width depending upon said convergence condition.