Memory device which receives an external reference voltage signal

• US 6,513,081 B2
• Filed: 07/26/2001
• Issued: 01/28/2003
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/916,493
• Publication Number:
  US 20020004867A1
• Time in Patent Office: 551 Days
• Field of Search: 710/107, 710/305, 711/105, 365/189.01, 365/189.02, 365/189.09
• US Class Current: 710/107
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory device and a method of operation of the memory device. The memory device includes an array of memory cells and a reference voltage input terminal to receive an external reference voltage. In addition, the memory device includes an input receiver, coupled to the reference voltage input terminal, to sample data from an external signal line using the external reference voltage.

Claims

1. A dynamic random access memory device including an array of dynamic memory cells, wherein the memory device comprises:

a reference voltage input terminal to receive an external reference voltage; and

an input receiver, coupled to the reference voltage input terminal, to sample data from an external signal line using the external reference voltage.

2. The memory device of claim 1 wherein the external signal line is one of a plurality of signal lines of an external bus.

3. The memory device of claim 2 wherein control information, address information and the data are multiplexed over the external bus.

4. The memory device of claim 1 further including a clock receiver to receive an external clock signal, wherein the input receiver samples the data synchronously with respect to the external clock signal.

5. The memory device of claim 4 wherein the input receiver samples a first portion of the data in response to a rising edge transition of the external clock signal, and the input receiver samples a second portion of the data in response to a falling edge transition of the external clock signal.

6. The memory device of claim 4 wherein the input receiver further includes:

a first latch to sample a first portion of the data from the external signal line in response to a rising edge transition of the external clock signal; and

a second latch to sample a second portion of the data from the external signal line in response to a falling edge transition of the external clock signal.

7. The memory device of claim 1, further including a pad to couple the input receiver to the external signal line, wherein the input receiver further includes:

a first latch including;

a first input coupled to the pad; and

a second input coupled to the reference voltage input terminal.

8. The memory device of claim 7 wherein the input receiver further includes:

a second latch including;

a first input coupled to the pad; and

a second input coupled to the reference voltage input terminal.

9. The memory device of claim 1 wherein the input receiver receives an internally buffered version of the external reference voltage.

10. The memory device of claim 9 wherein the internally buffered version of the external reference voltage includes an offset.

11. The memory device of claim 9 further including a buffer coupled to the reference voltage input terminal and the input receiver to generate the internally buffered version of the external reference voltage.

12. The memory device of claim 1 wherein the external signal line is terminated by a resistor.

13. A method of operation of a dynamic random access memory device, wherein the memory device includes an array of dynamic memory cells, wherein the method comprises:

receiving an external reference voltage; and

sampling data from an external signal line, wherein the data is sampled using the external reference voltage.

14. The method of claim 13 further including buffering the external reference voltage to generate an internal reference voltage, wherein the data is sampled from the external signal line using the internal reference voltage.

15. The method of claim 14 wherein the internal reference voltage includes an offset relative to the external reference voltage.

16. The method of claim 13 further including receiving an external clock signal, wherein the data is sampled synchronously with respect to the external clock signal.

17. The method of claim 16 wherein a first portion of the data is sampled on a rising edge transition of the external clock signal and a second portion of the data is sampled on a falling edge transition of the external clock signal.

18. The method of claim 13 further including sampling address information from the external signal line, wherein the address information is sampled using the external reference voltage.

19. The method of claim 13 wherein the external signal line is one of a plurality of signal lines of an external bus.

20. The method of claim 19 wherein control information and address information are multiplexed over the external bus.

21. The method of claim 20 further including receiving the control information and address information from the external bus.

22. A semiconductor memory device, including an array of memory cells, wherein the memory device comprises:

a reference voltage terminal to receive an external reference voltage;

a first input receiver, coupled to the reference voltage terminal, to sample a first data bit from a first external signal line using the external reference voltage; and

a second input receiver, coupled to the reference voltage terminal, to sample a second data bit from a second external signal line using the external reference voltage.

23. The memory device of claim 22 wherein:

the first input receiver samples a first address bit from the first external signal line using the external reference voltage; and

the second input receiver samples a second address bit from the second external signal line using the external reference voltage.

24. The memory device of claim 22 further including a third input receiver to sample a control bit from a third external signal line, the control bit initiating a write operation in the memory device.

25. The memory device of claim 24 wherein the control bit is included in an operation code.

26. The memory device of claim 25 wherein the operation code is sampled during a first clock cycle of an external clock signal, and the first data bit is sampled during a second clock cycle of the external clock signal.

27. The memory device of claim 22 wherein the first and second input receivers are coupled to a bus to receive control information and address information in a multiplexed format via the bus.

28. The memory device of claim 22 further including a clock receiver to receive an external clock signal, wherein the first input receiver samples the first data bit synchronously with respect to the external clock signal.

29. The memory device of claim 28 wherein the first input receiver further samples a third data bit from the first external signal line and wherein:

the first input receiver samples the first data bit in response to a rising edge transition of the external clock signal; and

the first input receiver samples the third data bit in response to a falling transition of the external clock signal.

30. The memory device of claim 29 further including a pad to couple the first input receiver to the first external signal line, wherein the first input receiver includes:

a first latch, coupled to the pad, to hold the first data bit sampled from the first external signal line; and

a second latch, coupled to the pad, to hold the third data bit sampled from the first external signal line.

31. The memory device of claim 22 further including a pad to couple the first input receiver to the first external signal line, wherein the first input receiver includes:

a first input, coupled to the pad, to receive the first data bit from the first external signal line via the pad; and

a second input coupled to the reference voltage terminal.

32. The memory device of claim 22 further including a buffer, coupled to the reference voltage terminal, to generate an internal reference voltage, wherein:

the first input receiver samples the first data bit using the internal reference voltage; and

the second input receiver samples the second data bit using the internal reference voltage.

33. The memory device of claim 22 wherein the array of memory cells includes dynamic random access memory cells.

34. The memory device of claim 22 wherein the array of memory cells includes static random access memory cells.

35. A dynamic random access memory device, including an array of dynamic memory cells, wherein the memory device comprises:

a reference voltage terminal to receive an external reference voltage; and

a first input receiver, coupled to the reference voltage terminal, to sample data from a first external signal line using an internally buffered version of the external reference voltage.

36. The memory device of claim 35 further including a reference voltage buffer, coupled to the reference voltage terminal and the first input receiver, to generate the internally buffered version of the external reference voltage.

37. The memory device of claim 35 wherein the first external signal line is included in a plurality of external signal lines of a bus.

38. The memory device of claim 37 wherein the first input receiver is included in a plurality of input receivers coupled to the bus, wherein the plurality of input receivers are configured to receive control information and address information in a multiplexed format via the bus.

39. The memory device of claim 35 further including a clock receiver to receive an external clock signal, wherein the first input receiver samples the data synchronously with respect to the external clock signal.

40. The memory device of claim 39 wherein:

the first input receiver samples a first portion of the data on a rising edge transition of the external clock signal; and

the first input receiver samples a second portion of the data on a falling edge transition of the external clock signal.

41. The memory device of claim 40 further including a pad to couple the first input receiver to the first external signal line, wherein the first input receiver includes:

a first input latch, coupled to the pad, to hold the first portion of data; and

a second input latch, coupled to the pad, to hold the second portion of data.

42. The memory device of claim 35 wherein the first input receiver samples address information from the first external signal line using the internally buffered version of the external reference voltage.

43. The memory device of claim 35 wherein the first input receiver samples control information from the first external signal line using the internally buffered version of the external reference voltage.

44. The memory device of claim 35 further including a second input receiver to sample control information from a second external signal line using the internally buffered version of the external reference voltage.

45. The memory device of claim 44 wherein the second input receiver is coupled to sample address information from the second external signal line using the internally buffered version of the external reference voltage.

46. The memory device of claim 45 further including a clock receiver to receive an external clock signal, wherein the address information is sampled on a first transition of the external clock signal and the control information is sampled on a second transition of the external clock signal.

47. A dynamic random access memory device, including an array of dynamic memory cells, wherein the memory device comprises:

a reference voltage terminal to receive an external reference voltage; and

a first input receiver coupled to the reference voltage terminal, wherein the first input receiver includes;

a first input terminal to sample data from a first external signal line; and

a second input terminal to receive an internally buffered version of the external reference voltage.

48. The memory device of claim 47 wherein the internally buffered version of the external reference voltage is offset from the external reference voltage.

49. The memory device of claim 47 wherein the first external signal line is included in a plurality of external signal lines of a bus.

50. The memory device of claim 49 wherein the first input receiver is included in a plurality of input receivers coupled to the bus, wherein the plurality of input receivers are configured to receive, in a multiplexed format, control and address information via the bus.

51. The memory device of claim 47 further including a clock receiver to receive an external clock signal, wherein the first input receiver samples the data synchronously with respect to the external clock signal.

52. The memory device of claim 51 wherein:

the first input receiver samples a first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and

the first input receiver samples a second portion of the data synchronously with respect to a falling edge transition of the external clock signal.

53. The memory device of claim 52 further including a pad to couple the first input receiver to the first external signal line, wherein the first input receiver includes:

a first input latch, coupled to the pad, to hold the first portion of the data; and

a second input latch, coupled to the pad, to hold the second portion of the data.

54. The memory device of claim 47 wherein the first input receiver samples address information from the first external signal line using the internally buffered version of the external reference voltage.

55. The memory device of claim 47 wherein the first input receiver samples control information from the first external signal line using the internally buffered version of the external reference voltage.

56. The memory device of claim 47 further including a second input receiver to sample control information from a second external signal line using the internally buffered version of the external reference voltage.

57. The memory device of claim 56 wherein the second input receiver samples address information from the second external signal line using the internally buffered version of the external reference voltage.