Method and apparatus for adjusting the performance of a synchronous memory system
First Claim
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1. A memory system comprising:
- an integrated circuit memory device including a clock synchronization circuit to synchronize transmission of data from the integrated circuit memory device with an external clock signal, wherein the clock synchronization circuit is turned based on operating information provided to the integrated circuit memory device;
a master device to control the integrated circuit memory device; and
a plurality of signal lines coupled to the master device and to the integrated circuit memory device, wherein the integrated circuit memory device receives the operating information from the master device via the plurality of signal lines.
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Abstract
A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.
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Citations
81 Claims
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1. A memory system comprising:
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an integrated circuit memory device including a clock synchronization circuit to synchronize transmission of data from the integrated circuit memory device with an external clock signal, wherein the clock synchronization circuit is turned based on operating information provided to the integrated circuit memory device;
a master device to control the integrated circuit memory device; and
a plurality of signal lines coupled to the master device and to the integrated circuit memory device, wherein the integrated circuit memory device receives the operating information from the master device via the plurality of signal lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of controlling an integrated circuit memory device in a memory system that includes a master device, wherein the integrated circuit memory device is coupled to the master device via a plurality of signal lines, the method comprising:
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generating operating information in the master device; and
sending the operating information from the master device via the plurality of signal lines to the integrated circuit memory device, wherein the integrated circuit memory device receives and stores the operating information, and wherein the integrated circuit memory device tunes a clock synchronization circuit using the operating information. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A memory device having an array of memory cells, the memory device comprising:
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a programmable register to store a value that specifies a data transfer rate; and
an interface circuit to output data to an external signal line at the data transfer rate specified by the value stored in the register. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A memory device having an array of memory cells, the memory device comprising:
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a register to store a code that specifies a range of data transfer rates; and
an interface circuit to output data to an external signal line at a transfer rate in the range of data transfer rates. - View Dependent Claims (53, 54, 55, 56, 57, 58, 59)
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60. A method of controlling a synchronous memory device, the memory device including a plurality of memory cells and a clock synchronization circuit, the method comprising:
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issuing information indicative of a data transfer rate to the memory device, wherein the memory device receives the information and adjusts the clock synchronization circuit using the information indicative of the data transfer rate; and
transmitting data to the memory device at a transfer rate indicates by the information issued to the memory device. - View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68, 69)
generating temperature information in a controller device; and
providing the temperature information to the memory device, wherein the memory device adjusts the clock synchronization circuit using the temperature information.
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64. The method of claim 60 wherein the information indicative of the data transfer rate is a binary code that is representative of one of a plurality of data transfer rates.
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65. The method of claim 60 wherein the information indicative of the data transfer rate is a binary code that specifies a range of data transfer rates.
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66. The method of claim 60 wherein the memory device is coupled to a bus having a bus length, the method further comprising:
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generating bus length information based on the bus length; and
providing the bus length information to the memory device.
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67. The method of claim 60 further comprising:
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detecting supply voltage information; and
providing supply voltage information to the memory device, wherein the memory device adjusts the clock synchronization circuit using the supply voltage information.
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68. The method of claim 60 further comprising detecting the system operating frequency information and generating the information indicative of a data transfer rate based on the system operating frequency information.
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69. The method of claim 60 wherein the information indicative of a data transfer rate is issued to the memory device using an analog signal.
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70. A method of operation in a synchronous memory device, the memory device including a plurality of memory cells, the method comprising:
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receiving, from a controller, a value specifying a frequency;
storing the value specifying the frequency in a programmable register on the memory device; and
outputting data at the frequency specified by the value stored in the programmable register. - View Dependent Claims (71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81)
decoding the value to generate an internal control signal; and
adjusting an internal clock synchronization circuit in response to the internal control signal.
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74. The method of claim 70 wherein the value is a binary code that is representative of one of a plurality of data transfer rates.
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75. The method of claim 70 wherein the memory device further comprises a clock synchronization circuit, the method further comprising adjusting the clock synchronization circuit based on the value stored in the programmable register.
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76. The method of claim 75 wherein the clock synchronization circuit comprises at least one of a delay lock loop circuit and a phase lock loop circuit.
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77. The method of claim 75 wherein a locking frequency range of the clock synchronization circuitry is adjusted in accordance with the value stored in the programmable register.
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78. The method of claim 70 further comprising generating an internal clock signal having a controlled phase relationship with an external clock signal.
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79. The method of claim 78 further comprising:
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detecting a phase differential between the external clock signal and the internal clock signal;
generating the internal clock signal using a plurality of delay elements; and
varying the amount of delay in each delay element based on the phase differential, to adjust the phase relationship between the internal clock signal and the external clock signal.
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80. The method of claim 70 further comprising:
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receiving supply voltage information from a controller;
storing the supply voltage information within the memory device; and
adjusting an internal clock synchronization circuit based on the supply voltage information.
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81. The method of claim 70 further comprising:
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receiving temperature information from a controller;
storing the temperature information within the memory device; and
adjusting an internal clock synchronization circuit based on the temperature information.
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Specification