Method and apparatus for adjusting the performance of a synchronous memory system

• US 6,513,103 B1
• Filed: 10/10/1997
• Issued: 01/28/2003
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Portmann, Clemenz, Chau, Pak Shing, Garlepp, Bruno Werner, Barth, Richard M., Tsern, Ely K., Stark, Donald C., Davis, Paul G., Donnelly, Kevin S.
• Primary Examiner(s): Ellis, Kevin L.
• Application Number:
  US08/948,774
• Time in Patent Office: 1,936 Days
• Field of Search: 711/104, 711/105, 711/154, 711/156, 711/167, 711/170, 710/8
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.

Claims

1. A memory system comprising:

an integrated circuit memory device including a clock synchronization circuit to synchronize transmission of data from the integrated circuit memory device with an external clock signal, wherein the clock synchronization circuit is turned based on operating information provided to the integrated circuit memory device;

a master device to control the integrated circuit memory device; and

a plurality of signal lines coupled to the master device and to the integrated circuit memory device, wherein the integrated circuit memory device receives the operating information from the master device via the plurality of signal lines.

2. The memory system of claim 1 wherein the operating information specifies a clock frequency of the external clock signal.

3. The memory system of claim 1 wherein the operating information specifies a frequency range from among a plurality of frequency ranges, the frequency range including a clock frequency of the external clock signal.

4. The memory system of claim 1 wherein the operating information specifies a period of the external clock signal.

5. The memory system of claim 1 wherein the master device further comprises a detector to determine the operating information, wherein the operating information specifies a temperature range.

6. The memory system of claim 1 wherein the operating information specifies a supply voltage.

7. The memory system of claim 1 wherein the operating information is representative of a length of at least one signal line of the plurality of signal lines.

8. The memory system of claim 1 wherein the integrated circuit memory device includes a detector to determine an operating temperature range of the integrated circuit memory device, wherein the clock synchronization circuit is tuned based on the operating temperature range and the operating information.

9. The memory system of claim 1, wherein the integrated circuit memory device includes a detector to determine a voltage range.

10. The memory system of claim 9 wherein the clock synchronization circuit is turned based on the voltage range and the operating information.

11. The memory system of claim 1 wherein the memory system is a synchronous memory system.

12. The memory system of claim 1 wherein the clock synchronization circuit is a delay locked loop.

13. The memory system of claim 1 wherein the clock synchronization circuit is a phase locked loop.

14. The memory system of claim 1 wherein the clock synchronization circuit includes a mixer, wherein the clock synchronization curcuit is turned on using the mixer.

15. The memory system of claim 14 wherein the clock synchronization circuit is turned to operate over a range of operating frequencies using the mixer, wherein an operating frequency within the range of operating frequencies is specified by the operating information.

16. The memory system of claim 1 wherein the plurality of signal lines includes first lines which are operated at a first data transfer rate, and second lines which are operated at a second data transfer rate, wherein the second data trnasfer rate is lower than the first data transfer rate.

17. The memory system of claim 16 wherein the integrated circuit memory device receives the operating information over the second lines, and wherein the data is transmitted over the first lines.

18. The memory system of claim 16 wherein the integrated circuit memory device receives the operating information over the first lines.

19. The memory system of claim 1 wherein the integrated circuit memory device further includes an n-bit register to store the system information.

20. The memory system of claim 19, wherein the operating information is stored in a portion of the n-bit register.

21. A method of controlling an integrated circuit memory device in a memory system that includes a master device, wherein the integrated circuit memory device is coupled to the master device via a plurality of signal lines, the method comprising:

generating operating information in the master device; and

sending the operating information from the master device via the plurality of signal lines to the integrated circuit memory device, wherein the integrated circuit memory device receives and stores the operating information, and wherein the integrated circuit memory device tunes a clock synchronization circuit using the operating information.

22. A method of controlling an integrated circuit memory device according to claim 21 wherein the operating information specifies frequency information.

23. A method of controlling an integrated circuit memory device according to claim 22 wherein the frequency information specifies an operating clock frequency of the memory system.

24. A method for controlling an integrated circuit memory device according to claim 22 wherein the frequency information specifies a frequency range from among a plurality of frequency ranges, the specified frequency range including an operating clock frequency of the memory system.

25. A method for controlling an integrated circuit memory device according to claim 22 wherein the frequency information specifies a period of an operating clock freqiency.

26. A method for controlling an integrated circuit memory device according to claim 21 wherein the operating information includes information specifying supply voltage.

27. A method of controlling an integrated circuit memory device according to claim 21 wherein the operating information represents a temperature range.

28. A method of controlling an integrated circuit memory device according to claim 21 wherein the master device includes a clock synchronization circuit to synchronize transmission of data from the master device to the integrated circuit memory device, wherein the method further includes tuning the clock synchronization circuit within the master device.

29. A method of controlling an integrated circuit memory device according to claim 21 wherein the operating information represents a length of at least one signal line of the plurality of signal lines.

30. A method of controlling an integrated circuit memory device according to claim 21 wherein the memory system is a synchronous memory system.

31. A method of controlling an integrated circuit memory device according to claim 21 wherein the master device includes a delay locked loop, the method further including tuning the delay locked loop using the operating information.

32. A method of controlling an integrated circuit memory device according to claim 21 wherein the master device includes a phase locked loop, the method further including tuning the phase locked loop using the operating information.

33. A method of controlling an integrated circuit memory device according to claim 32 wherein tuning the clock synchronization circuit of the integrated circuit memory device includes adjusting a locking frequency range of the clock synchronization circuit to include an operating clock frequency of the memory system.

34. A method of controlling an integrated circuit memory device according to claim 21 wherein the plurality of signal lines includes a first plurality of lines and a second plurality of lines, wherein the second plurality of lines is designed to be operated at a slower data transfer rate than the first plurality of lines.

35. A method of controlling an integrated circuit memory device according to claim 34 wherein tuning the clock synchronization circuit in the integrated circuit memory device reduces an amount of jitter of at least a first signal propagating on a first signal line of the first plurality of lines.

36. A method of controlling an integrated circuit memory device according to claim 34 wherein the operating information is sent over the second plurality of lines.

37. A method of controlling an integrated circuit memory device according to claim 34 wherein the operating information is sent over the first plurality of lines.

38. A method of controlling an integrated circuit memory device according to claim 21 wherein the master device stores the operating information in an n-bit register.

39. A method of controlling an integrated circuit memory device according to claim 38 wherein the operating information is stored in a subset of the n-bit register.

40. The method of claim 21 wherein the generating and sending of operating information is performed periodically.

41. The method of claim 21 wherein the operating information is sent during initialization of the memory system.

42. A memory device having an array of memory cells, the memory device comprising:

a programmable register to store a value that specifies a data transfer rate; and

an interface circuit to output data to an external signal line at the data transfer rate specified by the value stored in the register.

43. The memory device of claim 42 wherein the value is a binary code that is representative of one of a plurality of data transfer rates.

44. The memory device of claim 42 further comprising a circuit to store temperature information.

45. The memory device of claim 42 further comprising a clock synchronization circuit to receive an external clock signal and synchronize the outputting of data with the external clock signal.

46. The memory device of claim 45 wherein the clock synchronization circuit comprises one of a delay locked loop circuit and a phase locked loop circuit.

47. The memory device of claim 45 wherein the programmable register is coupled to the clock synchronization circuit and wherein the clock synchronization circuit is adjusted in accordance with the value stored within the programmable register.

48. The memory device of claim 47 wherein the clock synchronization circuit comprises a mixer circuit to vary a phase of an internal clock signal in response to the value stored in the programmable register.

49. The memory device of claim 42 further comprising decoder circuitry coupled to the programmable register to decode the value stored within the programmable register.

50. The memory device of claim 42 further comprising a circuit to store information indicative of a length of an external bus.

51. The memory device of claim 42 wherein the data is output synchronously with respect to an external clock signal.

52. A memory device having an array of memory cells, the memory device comprising:

a register to store a code that specifies a range of data transfer rates; and

an interface circuit to output data to an external signal line at a transfer rate in the range of data transfer rates.

53. The memory device of claim 52 wherein the code is representative of one of a plurality of data transfer rate ranges.

54. The memory device of claim 52 further comprising a circuit to store operating temperature information.

55. The memory device of claim 52 further comprsises an internal clock synchronization circuit to receive an external clock signal and synchronize the outputting of data with the external clock signal.

56. The memory device of claim 55 wherein the internal clock synchronization circuit comprises one of a delay locked loop circuit and a phase locked loop circuit.

57. The memory device of claim 55 wherein a frequency locking range of the clock synchronization circuit is varied in accordance with the code that specifies the range of data transfer rates.

58. The memory device of claim 52 further comprising decoder circuitry coupled to the register to decode the code stored within the register.

59. The memory device of claim 52 further comprising a circuit to store supply voltage information.

60. A method of controlling a synchronous memory device, the memory device including a plurality of memory cells and a clock synchronization circuit, the method comprising:

issuing information indicative of a data transfer rate to the memory device, wherein the memory device receives the information and adjusts the clock synchronization circuit using the information indicative of the data transfer rate; and

transmitting data to the memory device at a transfer rate indicates by the information issued to the memory device.

61. The method of claim 60 wherein the memory device stores the information indicative of the data transfer rate in a register on the memory device.

62. The method of claim 60 wherein the information indicative of the data transfer rate is issued to the memory device during initialization of the memory device.

63. The method of claim 60 further comprising:

generating temperature information in a controller device; and

providing the temperature information to the memory device, wherein the memory device adjusts the clock synchronization circuit using the temperature information.

64. The method of claim 60 wherein the information indicative of the data transfer rate is a binary code that is representative of one of a plurality of data transfer rates.

65. The method of claim 60 wherein the information indicative of the data transfer rate is a binary code that specifies a range of data transfer rates.

66. The method of claim 60 wherein the memory device is coupled to a bus having a bus length, the method further comprising:

generating bus length information based on the bus length; and

providing the bus length information to the memory device.

67. The method of claim 60 further comprising:

detecting supply voltage information; and

providing supply voltage information to the memory device, wherein the memory device adjusts the clock synchronization circuit using the supply voltage information.

68. The method of claim 60 further comprising detecting the system operating frequency information and generating the information indicative of a data transfer rate based on the system operating frequency information.

69. The method of claim 60 wherein the information indicative of a data transfer rate is issued to the memory device using an analog signal.

70. A method of operation in a synchronous memory device, the memory device including a plurality of memory cells, the method comprising:

receiving, from a controller, a value specifying a frequency;

storing the value specifying the frequency in a programmable register on the memory device; and

outputting data at the frequency specified by the value stored in the programmable register.

71. The method of claim 70 wherein the value is received by the memory during an initialization period.

72. The method of claim 70 wherein the data is output synchronously with respect to an external clock signal.

73. The method of claim 70 further comprising:

decoding the value to generate an internal control signal; and

adjusting an internal clock synchronization circuit in response to the internal control signal.

74. The method of claim 70 wherein the value is a binary code that is representative of one of a plurality of data transfer rates.

75. The method of claim 70 wherein the memory device further comprises a clock synchronization circuit, the method further comprising adjusting the clock synchronization circuit based on the value stored in the programmable register.

76. The method of claim 75 wherein the clock synchronization circuit comprises at least one of a delay lock loop circuit and a phase lock loop circuit.

77. The method of claim 75 wherein a locking frequency range of the clock synchronization circuitry is adjusted in accordance with the value stored in the programmable register.

78. The method of claim 70 further comprising generating an internal clock signal having a controlled phase relationship with an external clock signal.

79. The method of claim 78 further comprising:

detecting a phase differential between the external clock signal and the internal clock signal;

generating the internal clock signal using a plurality of delay elements; and

varying the amount of delay in each delay element based on the phase differential, to adjust the phase relationship between the internal clock signal and the external clock signal.

80. The method of claim 70 further comprising:

receiving supply voltage information from a controller;

storing the supply voltage information within the memory device; and

adjusting an internal clock synchronization circuit based on the supply voltage information.

81. The method of claim 70 further comprising:

receiving temperature information from a controller;

storing the temperature information within the memory device; and

adjusting an internal clock synchronization circuit based on the temperature information.