Method of making a III-nitride light-emitting device with increased light generating capability

• US 6,514,782 B1
• Filed: 12/22/1999
• Issued: 02/04/2003
• Est. Priority Date: 12/22/1999
• Status: Expired due to Term

• Current Assignee: Agilent Technologies Europe BV (Agilent Technologies, Inc.), Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Lumileds Lighting US LLC (Apollo Global Management, Inc.)
• Inventors: Wierer, Jonathan J. Jr., Rajkomar, Pradeep, Kish, Fred A. Jr., Steigerwald, Daniel A., Krames, Michael R
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/470,450
• Time in Patent Office: 1,140 Days
• Field of Search: 257/94, 257/96, 257/97, 257/99, 257/103, 257/106, 257/610, 257/13-15, 438/26-39, 438/46
• US Class Current: 438/22
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17106 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/641 : characterized by the materials
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.

Claims

1. A method for fabricating an inverted light emitting device, the method comprising:

depositing a III-nitride heterostructure on a growth structure;

electrically connecting an opaque p-electrode having a specific contact resistance less than 10<sup>−

2</sup> Ω

cm² and a light absorption less than 35%, and an n-electrode to a same side of the III-nitride heterostructure; and

attaching a submount to the p-electrode and the n-electrode;

wherein light is extracted through the growth structure.

2. A method, as defined in claim 1, wherein attaching the submount includes:

applying interconnect to a submount wafer; and

forming a joint between the p- and n-electrodes and the interconnect;

dicing the submount wafer to form a submount; and

attaching the submount to a package.

3. A method, as defined in claim 2, wherein attaching the submount further comprises dispensing underfill between the II-nitride heterostructure and the submount wafer prior to dicing the submount wafer.

4. A method, as defined in claim 2, wherein forming a joint comprises forming a eutectic bond between the p- and n-electrodes and the submount.

5. A method, as defined in claim 2, wherein forming a joint comprises forming a solder joint between the p- and n-electrodes and the submount.

6. A method, as defined in claim 2, wherein the interconnect comprises solder.

7. A method, as defined in claim 2, wherein the interconnect comprises a thermally and electrically conductive compound.

8. A method, as defined in claim 2, wherein the interconnect is selected from the group consisting of metals, metal alloys, and semiconductor-metal alloys.

9. A method, as defined in claim 1, wherein attaching further comprises:

applying interconnect to the p- and n-electrodes;

dicing a submount wafer to form a submount;

attaching the submount to a package; and

forming a joint between the interconnect and the submount.

10. A method, as defined in claim 9, further comprising dispensing underfill between the III-nitride heterostructure and the submount.

11. A method, as defined in claim 9, wherein forming a joint comprises forming a eutectic bond between the p- and n-electrodes and the submount.

12. A method, as defined in claim 9, wherein forming a joint comprises forming a solder joint between the p- and n-electrodes and the submount.

13. A method, as defined in claim 1, further comprising:

depositing an intermetal dielectric overlying the p- and n-electrodes, wherein the intermetal dielectric electrically isolates the p- and n-electrodes;

applying a sheet reflector overlying the intermetal dielectric; and

applying a barrier layer overlying the sheet reflector.

14. A method, as defined in claim 1, further comprising:

applying conductive interfaces to the p- and n-electrodes; and

patterning the conductive interfaces.

15. A method, as defined in claim 14, further comprising:

applying a dielectric overlying the p- and n-electrodes; and

patterning the dielectric.

16. A method, as defined in claim 14, wherein the conductive interface is a wettable metal.