CMOS image sensor n-type pin-diode structure

• US 6,514,785 B1
• Filed: 06/09/2000
• Issued: 02/04/2003
• Est. Priority Date: 06/09/2000
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiang, An-Min, Lee, Chi-Hsiang, Yeh, Wei-Kun, Yang, Hua-Yu
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEE, GRANVILL D
• Application Number:
  US09/590,125
• Time in Patent Office: 970 Days
• Field of Search: 438/57-59, 438/48, 438/7, 438/510-514, 438/519, 257/113-118, 257/184-186, 257/290-92
• US Class Current: 438/48
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes

Abstract

A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

Claims

1. A method of forming an image sensor comprising:

providing a partially processed semiconductor wafer containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors;

forming source/drain regions about the said gate electrode structures;

the area to be photodiode regions being masked during said forming of source/drain regions;

forming two photodiode regions of the same conductivity type as said source/drain regions and overlapping one of the source drain regions;

one of the photodiode regions being shallow and of high carrier density and the other being deeper and of a lower carrier density;

said source/drain regions, except for the areas of overlap, being masked during said forming of two photodiode regions;

depositing a blanket transparent insulating layer;

providing electrical contact through the transparent insulating layer to the gate structures, the overlapped source/drain regions and the photodiode regions.

2. The method of claim 1 wherein the said gate electrode structures are composed of polysilicon or polycide.

3. The method of claim 1 wherein the isolation region is composed of field oxide.

4. The methods of claim 1 wherein the semiconductor region is p-type and the source/drain regions are n-type.

5. The method of claim 1 wherein the semiconductor region is p-type silicon and the source/drain implant ions are arsenic and/or phosphorus.

6. The methods of claim 1 wherein the semiconductor region is n-type and the ions implanted to form the source/drain regions are acceptors.

7. The method of claim 1 wherein the semiconductor region is n-type silicon and the source/drain implant ions are boron and/or fluorine.

8. The method of claim 1 wherein the source/drain implant is accomplished in two stages;

the first, providing regions near the gate that are lightly doped and the second, deeper, but overlapping, highly doped regions.

9. The method of claim 1 wherein the semiconductor region is p-type silicon and the source/drain implant is accomplished in two stages;

the first being phosphorus to a dose of about 1E13 to 1E14 per cm2 at an energy of 40 to 70 keV and the second being arsenic to a dose of about 1E15 to 5E15 per cm2 at an energy of 35 to 65 keV.

10. The method of claim 1 wherein the semiconductor region is n-type silicon and the source/drain implant is accomplished in two stages;

the first being BF2 to a dose of about 8E12 to 5E13 per cm2 at an energy of 30 to 50 keV and the second being BF2 to a dose of about 1E15 to 5E15 per cm2 at an energy 30 to 50 keV.

11. The method of claim 1 wherein the width of the gate electrode is between 0.5 to 1.5 micrometers.

12. The method of claim 1 wherein the width of the source/drain regions is between 0.35 to 1.0 micrometers.

13. The method of claim 1 wherein the width of the overlap region is between about 0.3 to 0.7 micrometers.

14. The method of claim 1 wherein the semiconductor region is p-type and the photodiode implant ions are donors.

15. The method of claim 1 wherein the semiconductor region is p-type silicon and the photodiode implant ions are phosphorus;

to a dose of about 1E15 to 1E16 per cm2 at an energy of about 5 to 40 keV for the shallow photodiode region and to a dose of about 1E12 to 1E14 per cm2 at an energy of about 50 to 180 keV for the deeper photodiode region.

16. The method of claim 1 where in said blanket insulating layer is TEOS, BPTOES or PEoxide.

17. A method of forming an image sensor comprising:

providing a partially processed semiconductor wafer containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces;

forming a well of the opposite conductivity type of said semiconductor region to be deep, low carrier density photodiode region;

regions to be source/drain regions, except for the region of overlap, being masked during said forming of said well;

forming gate electrode structures some of which will serve as gate electrodes of image sensor transistors;

forming LDD source/drain regions about said gate electrode structures, with source/drain regions of image sensors being of the same conductivity type as said well, and one of the source/drain regions overlapping said well;

said well, except for region of overlap, being masked during said forming of LDD source/drain regions;

forming shallow, high density photodiode region overlapping said well and source/drain region;

said source/drain regions, except for region of overlap, being masked during said forming of high density photodiode region;

depositing a blanket transparent insulating layer;

providing electrical contact through said transparent insulating layer to the gate structures, the unoverlapped source/drain regions and the photodiode regions.

18. The method of claim 17 wherein said well is n-type.

19. The method of claim 17 wherein said well is formed by implantation of phosphorous to a dose of about 1E12 to 1E14 at energy of about 50 to 180 keV.

20. The method of claim 17 wherein said well is p-type.

21. The method of claim 17 wherein the semiconductor region is p-type silicon and the LDD source/drain implant ions are arsenic and phosphorus.

22. The methods of claim 17 wherein the semiconductor region is n-type and the source/drain regions are p-type.

23. The method of claim 17 wherein the semiconductor region is n-type silicon and the source/drain implant ions are boron, fluorine or boron fluoride.

24. The method of claim 17 wherein the source/drain implant is accomplished in two stages;

the first, provide Sightly doped regions near the gate and the second, deeper highly doped regions, insulating spacers, which can be TEOS, are formed between the two implant stages.

25. The method of claim 17 wherein the semiconductor region is p-type silicon and the source/drain implant is accomplished in two stages;

insulating spacers, which can be TEOS, being formed between the stages, the first stage being phosphorus to a dose of about 1E13 to 1E14 per cm2 at an energy of 40 to 70 keV and the second being arsenic to a dose of about 1E15 to 5E15 per cm2 at an energy of 35 to 65 keV.

26. The method of claim 17 wherein the semiconductor region is n-type silicon and the source/drain implant is accomplished in two stages;

the first being BF2 to a dose of about 8E12 to 5E13 per cm2 at an energy of 30 to 50 keV and the second being BF2 to a dose of about 1E15 to 5E15 per cm2 at an energy 30 to 50 keV, TEOS spacers being formed between the stages.

27. The method of claim 17 wherein the width of the gate electrode is between about 0.35 to 1.0 micrometers.

28. The method of claim 17 wherein the width of the source/drain regions is between about 0.5 to 1.5 micrometers.

29. The method of claim 17 wherein the width of the overlap region is between about 0.3 to 0.7 micrometers.

30. The method of claim 17 wherein the semiconductor region is p-type and the shallow photodiode implant ions are donors.

31. The method of claim 17 wherein the semiconductor region is p-type silicon and the shallow photodiode implant ions are phosphorus to a dose of about 1E15 to 5E16 per cm2 at an energy of 5 to 40 keV.

32. The method of claim 19 wherein said blanket insulating layer is TEOS, BPTEOS or PEoxide.