Method of forming shallow trench
First Claim
1. A method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate, each said deep trench capacitor construction having a collar construction and a conductor construction, comprising steps of:
- (a) defining a mask by forming a mask layer on said semiconductor substrate having said deep trench capacitor constructions;
(b) performing a first etching process with respect to said specific region uncovered by said mask so as to form a first depth trench, said first etching process having a relatively high selectivity ratio of said conductor construction relative to said mask; and
(c) performing a second etching process with respect to said first depth trench so as to form a second depth trench, said second etching process having a selectivity ratio of said conductor construction relative to said collar construction substantially close to 1.
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Accused Products
Abstract
A method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate, each the deep trench capacitor construction having a collar construction and a conductor construction is provided. The method of forming a shallow trench includes steps of (a) defining a mask by forming a mask layer on the semiconductor substrate which has the deep trench capacitor constructions, (b) performing a first etching process with respect to the regions, which is not covered by the mask, so as to form a first depth trench, in which the first etching process has a relatively high selectivity ratio of the conductor construction relative to the mask, and (c) performing a second etching process with respect to the first depth trench so as to form a second depth trench, in which the second etching process has a selectivity ratio of the conductor construction relative to the collar construction substantially close to 1.
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Citations
12 Claims
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1. A method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate, each said deep trench capacitor construction having a collar construction and a conductor construction, comprising steps of:
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(a) defining a mask by forming a mask layer on said semiconductor substrate having said deep trench capacitor constructions;
(b) performing a first etching process with respect to said specific region uncovered by said mask so as to form a first depth trench, said first etching process having a relatively high selectivity ratio of said conductor construction relative to said mask; and
(c) performing a second etching process with respect to said first depth trench so as to form a second depth trench, said second etching process having a selectivity ratio of said conductor construction relative to said collar construction substantially close to 1. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
a silicon oxide layer formed on said semiconductor substrate;
a silicon nitride layer formed on said silicon oxide layer; and
a doped silicon oxide layer formed on said silicon nitride layer.
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6. The method according to claim 5 wherein said doped silicon oxide layer is a BSG (borosilicate glass) layer.
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7. The method according to claim 1 wherein said first etching process has a relatively high selectivity ratio of Silicon relative to silicon oxide.
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8. The method according to claim 1 wherein said second etching process has a selectivity ratio of said polycrystalline silicon relative to said silicon oxide substantially close to 1.
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9. The method according to claim 8 wherein said second etching process is a plasma etching process.
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10. The method according to claim 9 wherein the reacting gas of said plasma etching process comprises trifluoromethane (CHF3), tetrafluoromethane (CF4), and chlorine (Cl2).
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11. The method according to claim 8 wherein the depth of the bottom of said first depth trench is the STI target depth and is less then that of the top of said collar construction.
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12. The method according to claim 7 wherein the reacting gas of said first etching process comprises hydrogen bromide (HBr), chlorine (Cl2), oxygen (O2), and inert gas.
Specification