Method of making a TFT array with photo-imageable insulating layer over address lines
First Claim
1. A liquid crystal display device comprising:
- a substrate;
an array of transistors on said substrate;
a plurality of gate and data lines connected to said transistors;
an array of pixel electrodes on said substrate;
a plurality of pixel electrodes overlapping at least one of the gate and data lines; and
a photo-imageable insulating layer on said substrate between said gate and data lines and said pixel electrodes at least in the areas of overlap and areas adjacent source electrodes of the transistors, wherein said photo-imageable insulating layer has a dielectric constant less than about 5.0, and a first group of contact vias defined therein by photo-imaging, wherein said pixel electrodes are in electrical communication with corresponding transistor source electrodes through corresponding contact vias of said first group that are defined in said insulating layer.
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Abstract
This invention is related to a thin film transistor (TFT) array and method of making same, for use in an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The TFT array and corresponding display are made by forming the TFTs and corresponding address lines on a substrate, coating the address lines and TFTs with a photo-imageable insulating layer which acts as a negative resist, exposing portions of the insulating layer with UV light which are to remain on the substrate, removing non-exposed areas of the insulating layer so as to form contact vias, and depositing pixel electrodes on the substrate over the insulating layer so that the pixel electrodes contact respective TFT source electrodes through the contact vias. The resulting display has an increased pixel aperture ratio because the pixel electrodes are formed over the insulating layer so as to overlap portions of the array address lines.
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Citations
13 Claims
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1. A liquid crystal display device comprising:
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a substrate;
an array of transistors on said substrate;
a plurality of gate and data lines connected to said transistors;
an array of pixel electrodes on said substrate;
a plurality of pixel electrodes overlapping at least one of the gate and data lines; and
a photo-imageable insulating layer on said substrate between said gate and data lines and said pixel electrodes at least in the areas of overlap and areas adjacent source electrodes of the transistors, wherein said photo-imageable insulating layer has a dielectric constant less than about 5.0, and a first group of contact vias defined therein by photo-imaging, wherein said pixel electrodes are in electrical communication with corresponding transistor source electrodes through corresponding contact vias of said first group that are defined in said insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification