Thin oxide anti-fuse
First Claim
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1. An anti-fuse of a semiconductor device, the semiconductor device having design rules, the anti-fuse comprising:
- an active region in a semiconductor substrate;
a channel region adjacent to the active region in the substrate;
a gate oxide layer on a main surface of the substrate above the channel region; and
a conductive gate on the gate oxide layer, the gate having about a minimum dimension according to the design rules of the semiconductor device;
wherein the gate, channel region and active region are arranged such that the gate oxide fails when a programming voltage is applied between the gate and the active regions wherein the active region is of a first conductivity type, further comprising a second active region of a second conductivity type, wherein the second active region and the gate are electrically connected.
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Abstract
A programmable anti-fuse is formed simultaneously with transistors and other devices on a semiconductor substrate. Embodiments include an anti-fuse comprising a doped active region in the substrate, such as an n+ region, a gate oxide layer, and a gate, such as polysilicon, of a minimum size according to design rules. The anti-fuse is programmed by passing a current through it sufficient to cause its gate oxide layer to fail. The inventive anti-fuse is formed by simply altering the patterning of layers that need to be formed for other devices on the substrate. Therefore, it is formed without added manufacturing costs.
86 Citations
8 Claims
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1. An anti-fuse of a semiconductor device, the semiconductor device having design rules, the anti-fuse comprising:
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an active region in a semiconductor substrate;
a channel region adjacent to the active region in the substrate;
a gate oxide layer on a main surface of the substrate above the channel region; and
a conductive gate on the gate oxide layer, the gate having about a minimum dimension according to the design rules of the semiconductor device;
wherein the gate, channel region and active region are arranged such that the gate oxide fails when a programming voltage is applied between the gate and the active regions wherein the active region is of a first conductivity type, further comprising a second active region of a second conductivity type, wherein the second active region and the gate are electrically connected. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An anti-fuse of a semiconductor device, the semiconductor device having design rules, the anti-fuse comprising:
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an active region in a semiconductor substrate;
a channel region adjacent to the active region in the substrate;
a gate oxide layer on a main surface of the substrate above the channel region; and
a conductive gate on the gate oxide layer, the gate having about a minimum dimension according to the design rules of the semiconductor device;
wherein the gate, channel region and active region are arranged such that the gate oxide fails when a programming voltage is applied between the gate and the active region;
wherein the gate comprises a donut-shaped portion having a substantially rectangular inner opening above the active region, the inner opening having substantially 90-degree corners.
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Specification
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Current AssigneeMonterey Research, LLC (Vector Capital Corporation)
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsWollesen, Donald L.
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Primary Examiner(s)Loke, Steven
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Assistant Examiner(s)Kang, Donghee
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Application NumberUS09/698,485Time in Patent Office827 DaysField of Search257/50, 257/530, 257/410, 257/529, 257/532, 438/600, 438/131, 438/467, 438/957, 438/281, 438/333, 365/96, 365/225.7US Class Current257/530CPC Class CodesH01L 23/5252 comprising anti-fuses, i.e....H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
