Semiconductor device with FET MESA structure and vertical contact electrodes

• US 6,515,348 B2
• Filed: 05/08/2001
• Issued: 02/04/2003
• Est. Priority Date: 05/10/2000
• Status: Expired due to Fees

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Hijzen, Erwin A., Hueting, Raymond J. E.
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Fenty, Jesse A
• Application Number:
  US09/851,441
• Publication Number:
  US 20010040273A1
• Time in Patent Office: 637 Days
• Field of Search: 257/330-332, 257/342-347, 257/622-624
• US Class Current: 257/623
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of the body region (3a) between the source and drain regions. The device has one or more mesa structures (100) having end and side walls (100a to 100d). The body region (3a) extends between and meets at least the side walls (100c and 100d) of the mesa structure. The gate structure (7a, 7b) extends along and between the side walls such that the conduction channel accommodating portion (3b) extends along and between the side walls (100c and 100d). The source and drain regions (5 and 6) meet respective end walls (100a and 100b) of the mesa structure and/or its side walls (100c and 100d). At the mesa walls, a source electrode (S) contacts the source region (5) and a drain electrode (D) contacts the drain region (6). (FIGS. 12 and 13)

Claims

1. A semiconductor device comprising a semiconductor body comprising a field effect device, the semiconductor body having source and drain regions spaced apart by a body, region, the field effect device having a gate structure for controlling a conduction channel in a conduction channel accommodating portion of the body region between the source and drain regions, wherein the field effect device comprises a mesa structure having end walls and side walls, the source and drain regions meet respective end walls and part of the side walls of the mesa structure, source and drain electrodes contact the source and drain regions respectively along a depth of the walls of the mesa structure, the body region extends between and meets the side walls of the mesa structure, and the gate structure extends along and between the side walls such that the conduction channel accommodating portion extends along and between the side walls.

2. A semiconductor device according to claim 1, wherein the gate structure is provided within a trench in the mesa structure.

3. A semiconductor device according to claim 2, wherein the gate structure has first and second end regions in the trench that are surrounded by source and drain regions respectively.

4. A semiconductor device according to claim 2, wherein the trench has first and second end walls connected by side walls, and respective source and drain regions are provided at opposite ends of the trench such that the source region extends along part of one trench side wall adjacent the first trench end wall, along the first trench end wall and along part of the other trench side wall adjacent the first trench end walls and the drain region extends along part of one trench side wall adjacent the second trench end wall, along the second trench end wall and along part of the other trench side wall adjacent the second trench end wall.

5. A semiconductor device according to claim 2, wherein the gate structure extends from one trench end wall to the other.

6. A semiconductor device according to claim 2, wherein the gate structure has a conductive gate region that substantially fills the trench.

7. A semiconductor device as claimed in claim 1, wherein the walls of the mesa structure have a depth that is deeper than the walls of the trench in which the gate structure is provided.

8. A semiconductor device according to claim 7, wherein the gate structure and the source and drain electrodes extend from the mesa structure onto a support region supporting the mesa structure.

9. A semiconductor device as claimed in claim 1, wherein the source and drain electrodes contact the source and drain regions over the whole depth of the walls of the mesa structure.

10. A semiconductor device as claimed in claim 1, wherein a series of alternating source and drain regions is provided along the length of the mesa structure to form respective field effect devices that are connected in parallel to provide a higher power device.

11. A semiconductor device as claimed in claim 1, and comprising a plurality of the mesa structures located side-by-side, with the field effect devices of the respective mesa structures connected in parallel to provide a higher power device.

12. A semiconductor device according to claim 1, wherein the gate structure extends on top of and over the side walls of the mesa structure.

13. A semiconductor device according to claim 1, wherein the source and drain electrodes extend along each surface of the source and drain regions, respectively, that forms part of the exposed surface area of the mesa structure

14. A semiconductor device according to claim 1, wherein the gate structure comprises an insulated gate structure.

15. A semiconductor device comprising a field effect device formed as a mesa structure with source and drain regions at opposite ends of a trench formed in the mesa structure, a gate structure provided within the trench on bottom and side walls of the trench to control a conduction channel between the source and drain regions, and source and drain electrodes that extend along and contact a depth of the source and drain regions.

16. A semiconductor device comprising a semiconductor body that comprises a field effect device, wherein the semiconductor body comprises source and drain regions spaced apart by a body region, and wherein the field effect device comprises:

a gate structure for controlling a conduction channel in a conduction channel accommodating portion of the body region between the source and drain regions;

a mesa structure having end walls and side walls, wherein the source and drain regions meet respective end walls and part of the side walls of the mesa structure, and wherein the gate structure extends along and between the side walls such that the conduction channel accommodating portion extends along and between the side walls; and

source and drain electrodes contacting the source and drain regions along a depth of the source and drain regions.

17. The semiconductor device of claim 16, wherein the gate structure is provided within a trench in the mesa structure, wherein the trench has end walls and side walls, and wherein the source and drain regions contact respective end walls of the trench.

18. The semiconductor device of claim 17, wherein the gate structure comprises a conductive region that substantially fills a volume of the trench.

19. The semiconductor device of claim 16, wherein the gate structure extends on top of and over the side walls of the mesa structure.

20. The semiconductor device of claim 16, wherein the gate structure and the source and drain electrodes extend from the mesa structure onto a support region supporting the mesa structure.