Sub-cap and method of manufacture therefor in integrated circuit capping layers
First Claim
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1. An integrated circuit comprising:
- a semiconductor substrate having a semiconductor device provided thereon;
a dielectric layer on the semiconductor substrate and having an opening provided therein;
a barrier layer lining the opening;
a conductor core over the barrier layer, the conductor core filling the opening and connected to the semiconductor device;
two sub-caps self-aligned over the conductor core and formed into electromigration reducing compounds with the conductor core; and
a capping layer over the sub-cap and the dielectric layer.
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Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening, and a conductor core fills the opening over the barrier layer. Self-aligned sub-caps of silicide and/or oxides are formed over the conductor core and then capped by a capping layer which covers the sub-caps and the channel dielectric layer.
29 Citations
14 Claims
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1. An integrated circuit comprising:
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a semiconductor substrate having a semiconductor device provided thereon;
a dielectric layer on the semiconductor substrate and having an opening provided therein;
a barrier layer lining the opening;
a conductor core over the barrier layer, the conductor core filling the opening and connected to the semiconductor device;
two sub-caps self-aligned over the conductor core and formed into electromigration reducing compounds with the conductor core; and
a capping layer over the sub-cap and the dielectric layer. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit comprising:
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a silicon substrate having a semiconductor device provided thereon;
a device oxide layer on the semiconductor substrate and having a channel opening provided therein;
a barier layer lining the channel opening of a material selected from a group consisting of tantalum, titanium, tungsten, the nitrides thereof, and combinations thereof;
a seed layer linig the metal barrier layer of a material selected from a group consisting of copper, copper-base alloys, aluminum, gold, gold-base alloys, silver, silver-base alloys, and a combintion thereof;
a conductor core of a material selected from a group consisting of copper, copper-base alloys, aluminum, gold, gold-base alloys, silver, silver-base alloys, and a combination thereof filling the channel opening and connected to the semiconductor device;
a first sub-cap self-aligned over the conductor core of a silicide and formed into an electromigration reducing silicide compound with the conductor core;
a second sub-cap self-aligned over the conductor core of an oxide and formed into an electromigration reducing oxide compound with the conductor core; and
a capping layer of a nitride over the first and second sub-caps and the dielectric layer. - View Dependent Claims (7, 8)
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9. A method of manufacturing an integratd circuit comprising the steps of:
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providing a semiconductor substrate having a semiconductor device provided thereon;
forming a dielectric layer on the smiconductor substrate;
forming a opening in the dielectric layer;
depositing a barier layer to line the opening;
depositing a conductor core over the barrier layer to fill the opening and connect to the semiconductor device;
planarizing the conductor core and the barrier layer to be co-planar with the dielectric layer;
forming a first sub-cap self-aligned over the conductor core and forming a first electromigration reducing compound with the conductor core;
forming a second sub-cap self-aligned over the first sub-cap and forming a second electromigration reducing compound with the conductor core; and
depositing a capping layer over the sub-caps and the dielectric layer. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification