Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of copper

• US 6,515,368 B1
• Filed: 12/07/2001
• Issued: 02/04/2003
• Est. Priority Date: 12/07/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lopatin, Sergey, Nickel, Alexander H.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/016,410
• Time in Patent Office: 424 Days
• Field of Search: 251/751, 251/752, 251/758, 251/760, 251/761, 251/762, 251/764, 251/767, 251/775
• US Class Current: 257/762
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu—Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu—Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.

Claims

1. A semiconductor device, having a first interim reduced-oxygen copper-zinc alloy (Cu—

Zn) thin film formed on a copper (Cu) surface and a second interim reduced-oxygen Cu—

Zn alloy thin film formed on a Cu-fill, both films being formed by electroplating the Cu surface and the Cu-fill, respectively, in a chemical solution, comprising;

a semiconductor substrate having a via; and

an encapsulated dual-inlaid interconnect structure formed and disposed in said via, said interconnect structure comprising;

at least one Cu surface formed in said via;

a first interim reduced-oxygen Cu—

Zn alloy thin film formed and disposed on the at least one Cu surface;

a Cu-fill formed and disposed on said first interim reduced-oxygen Cu—

Zn alloy thin film; and

a second interim reduced-oxygen Cu—

Zn alloy thin film formed and disposed on the Cu-fill.

2. A semiconductor device, having a first interim reduced-oxygen copper-zinc (Cu—

Zn) alloy thin film formed on a copper (Cu) surface and a second interim reduced-oxygen Cu—

Zn alloy thin film formed on a Cu-fill, both films being formed by electroplating the Cu surface and the Cu-fill, respectively, in a chemical solution, fabricated by a method comprising the steps of;

providing a semiconductor substrate having a Cu surface formed in a via;

providing a chemical solution;

electroplating the Cu surface in the chemical solution, thereby forming a first interim Cu—

Zn alloy thin film on the Cu surface;

rinsing the first interim Cu—

Zn alloy thin film in a solvent;

drying the first interim Cu—

Zn alloy thin film under a gaseous flow;

annealing the first interim Cu—

Zn alloy thin film formed on the Cu surface, thereby forming a first interim reduced-oxygen Cu—

Zn alloy thin film;

filling the via with Cu on the first interim reduced-oxygen Cu—

Zn alloy thin film, thereby forming a Cu-fill;

annealing the Cu-fill, the first interim reduced-oxygen Cu—

Zn alloy thin film, and the Cu surface;

subjecting the annealed Cu-fill, the first interim reduced-oxygen Cu—

Zn alloy thin film, and the Cu surface to a process selected from a group consisting essentially of;

process (1) comprising the steps of;

electroplating the annealed Cu-fill in the chemical solution, thereby forming a second interim Cu—

Zn alloy thin film on the annealed Cu-fill;

rinsing the second interim Cu—

Zn alloy thin film in a solvent;

drying the second interim Cu—

Zn alloy thin film under a gaseous flow;

annealing second interim Cu—

Zn alloy thin film formed on the Cu-fill, thereby diffusing a plurality of Zn ions from the second interim Cu—

Zn alloy thin film into the Cu-fill, and thereby forming a second interim reduced-oxygen Cu—

Zn alloy thin film comprising the second interim Cu—

Zn alloy thin film as well as an upper portion of the Cu-fill; and

planarizing second interim reduced-oxygen Cu—

Zn alloy thin film, the Cu-fill, the first interim reduced-oxygen Cu—

Zn alloy thin film, and the Cu surface, thereby forming an encapsulated dual-inlaid interconnect structure; and

process (2) comprising the steps of;

planarizing the Cu-fill, the first interim reduced-oxygen Cu—

Zn alloy thin film, and the Cu surface, thereby forming an intermediate planarized surface;

depositing a Cu layer on the intermediate planarized surface;

electroplating the Cu layer in the chemical solution, thereby forming a second interim Cu—

Zn alloy thin film on the Cu layer;

rinsing the second interim Cu—

Zn alloy thin film in a solvent;

drying the second interim Cu—

Zn alloy thin film under a gaseous flow;

annealing second interim Cu—

Zn alloy thin film formed on the Cu layer, thereby diffusing a plurality of Zn ions from the second interim Cu—

Zn alloy thin film through the Cu layer and into the Cu-fill, and thereby forming a second interim reduced-oxygen Cu—

Zn alloy thin film comprising the second interim Cu—

Zn alloy thin film, the Cu layer, and an upper portion of the Cu-fill; and

planarizing the annealed second interim reduced-oxygen Cu—

Zn alloy thin film, the Cu layer, the Cu-fill, the first interim reduced-oxygen Cu—

Zn alloy thin film, and the Cu surface, thereby forming an encapsulated dual-inlaid interconnect structure; and

completing formation of the semiconductor device.

3. A device, as recited in claim 2,

wherein the chemical solution is nontoxic and aqueous, and

wherein the chemical solution comprises:

at least one zinc (Zn) ion source for providing a plurality of Zn ions;

at least one copper (Cu) ion source for providing a plurality of Cu ions;

at least one complexing agent for complexing the plurality of Cu ions;

at least one pH adjuster;

at least one wetting agent for stabilizing the chemical solution, all being dissolved in a volume of deionized (DI) water.

4. A device, as recited in claim 3, wherein the at least one zinc (Zn) ion source comprises at least one zinc salt selected from a group consisting essentially of zinc acetate ((CH₃CO₂)₂Zn), zinc bromide (ZnBr₂), zinc carbonate hydroxide (ZnCO₃·

2Zn(OH)₂), zinc dichloride (ZnCl₂), zinc citrate ((O₂CCH₂C(OH)(CO₂)CH₂CO₂)₂Zn₃), zinc iodide (ZnI₂), zinc L-lactate ((CH₃CH(OH)CO₂)₂Zn), zinc nitrate (Zn(NO₃)₂), zinc stearate ((CH₃(CH₂)₁₆CO₂)₂Zn), zinc sulfate (ZnSO₄), zinc sulfide (ZnS), zinc sulfite (ZnSO₃), and their hydrates.

5. A device, as recited in claim 3, wherein the at least one copper (Cu) ion source comprises at least one copper salt selected from a group consisting essentially of copper(I) acetate (CH₃CO₂Cu), copper(II) acetate ((CH₃CO₂)₂Cu), copper(I) bromide (CuBr), copper(II) bromide (CuBr₂), copper(II) hydroxide (Cu(OH)₂), copper(II) hydroxide phosphate (Cu₂(OH)PO₄), copper(I) iodide (CuI), copper(II) nitrate ((CuNO₃)₂), copper(II) sulfate (CuSO₄), copper(I) sulfide (Cu₂S), copper(II) sulfide (CuS), copper(II) tartrate ((CH(OH)CO₂)₂Cu), and their hydrates.

6. A device, as recited in claim 2,

wherein said electroplating step comprises using an electroplating apparatus, and

wherein said electroplating apparatus comprises:

(a) a cathode-wafer;

(b) an anode;

(c) an electroplating vessel; and

(d) a voltage source.

7. A device, as recited in claim 6,

wherein the cathode-wafer comprises the Cu surface, and

wherein the anode comprises at least one material selected from a group consisting essentially of copper (Cu), a copper-platinum alloy (Cu—

Pt), titanium (Ti), platinum (Pt), a titanium-platinum alloy (Ti—

Pt), an anodized copper-zinc alloy (Cu—

Zn), a platinized titanium (Pt/Ti), and a platinized copper-zinc (Pt/Cu—

Zn).

8. A device, as recited in claim 2,

wherein said semiconductor substrate further comprises a barrier layer formed in the via under said Cu surface, and

wherein the barrier layer comprises at least one material selected from a group consisting essentially of titanium silicon nitride (Ti_xSi_yN_z), tantalum nitride (TaN), and tungsten nitride (W_xN_y).

9. A device, as recited in claim 8,

wherein said semiconductor substrate further comprises an underlayer formed on the barrier layer,

wherein said underlayer comprises at least one material selected from a group consisting essentially of tin (Sn) and palladium (Pd), and

wherein said Cu surface is formed over said barrier layer and on said underlayer.

10. A device, as recited in claim 9,

wherein said underlayer comprises a thickness range of approximately 10 Å

to approximately 30 Å

,

wherein said barrier layer comprises a thickness range of approximately 10 Å

to approximately 30 Å

,

wherein said Cu surface comprises a thickness range of approximately 100 Å

to approximately 300 Å

, and

wherein said first interim Cu—

Zn alloy thin film comprises a thickness range of approximately 100 Å

to approximately 2000 Å

.