Semiconductor integrated circuit and semiconductor integrated circuit device

• US 6,515,511 B2
• Filed: 02/16/2001
• Issued: 02/04/2003
• Est. Priority Date: 02/17/2000
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sugibayashi, Tadahiko, Mogami, Tohru
• Primary Examiner(s): LE, DON P
• Application Number:
  US09/785,089
• Publication Number:
  US 20010015450A1
• Time in Patent Office: 718 Days
• Field of Search: 326/37-41, 326/101-103
• US Class Current: 326/41
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.

Claims

1. A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein:

each of the basic cells includes a wire selection portion and a logic gate portion,

the wire selection portion having at least one thin film transistor placed in an interlayer insulating film over a semiconductor substrate,

the logic gate portion has a programmable logic gate and a memory for programming the programmable logic gate,

the wire selection portion has a wire switch and an input-output switch,

the wire switch is connected to the signal bus and the memory, and

the input-output switch is connected to the signal bus, the memory and the programmable logic gate,

each of the wire switch and input-output switch being controlled by a data signal stored in the memory.

2. A circuit as claimed in claim 1, wherein:

the data signal is written into the memory by the use of one of a ROM, an EPROM, and an EEPROM when a power supply is introduced.

3. A circuit as claimed in claim 1, wherein:

the memory comprises an SRAM, a DRAM, a ROM, an EPROM, and an EEPROM.

4. A circuit as claimed in claim 1, wherein:

the signal bus comprises a Y-direction signal bus having first wiring lines and a X-direction signal bus having second wiring lines,

the wire switch has first transfer gates which are placed between the first wiring lines and the second wiring lines,

a wire connection between the Y-direction signal bus and the X-direction signal bus is changed by the first transfer gate.

5. A circuit as claimed in claim 4, wherein:

the first transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor so as to structure the wire selection portion in a three-dimensional form.

6. A circuit as claimed in claim 4, wherein:

the first thin film transistor has a first gate,

the first gate is connected to the memory,

the memory is driven by a voltage higher than a power supply voltage.

7. A circuit as claimed in claim 4, wherein:

the programmable logic gate has an input terminal and an output terminal,

the input-output switch has second transfer gates which are placed between the second wiring lines, and

a wire connection between the X-direction signal bus and the input terminal and the output terminal is changed by the second transfer gate.

8. A circuit as claimed in claim 6, wherein:

the second transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor so as to structure the wire selection portion in a three-dimensional form.

9. A circuit as claimed in claim 6, wherein:

the second thin film transistor has a second gate,

the second gate is connected to the memory,

the memory is driven by a voltage higher than a power supply voltage.

10. A circuit as claimed in claim 1, wherein:

the programmable logic gate comprises;

a switch portion which has a pair of third transfer gates,

a level converter which is connected to one of the third transfer gates;

an inverter which is connected to another one of the third transfer gates, and

an output buffer which is given with an output of the switch portion.

11. A circuit as claimed in claim 10, wherein:

the third transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor so as to structure the logic gate portion in a three-dimensional form.

12. A circuit as claimed in claim 1, wherein:

a repeater is inserted between the basic cells.

13. A circuit as claimed in claim 1, wherein:

the basic cell comprises a neuron cell.

14. A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein:

each of the basic cells includes a wire selection portion and a logic gate portion having transfer gates,

the logic gate portion has a fixed logic gate and a memory,

the wire selection portion has a wire switch and an input switch,

the wire switch is connected to the signal bus, the input switch, and the memory,

the input switch is connected to the signal bus and the fixed logic gate, and

the fixed logic gate is connected to the signal bus,

each of the wire switch and the input switch being controlled by a data signal stored in the memory.

15. A circuit as claimed in claim 14, wherein:

the memory comprises an SRAM, a DRAM, a ROM, an EPROM, and an EEPROM.

16. A circuit as claimed in claim 14, wherein:

the transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor.

17. A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein:

each of the basic cells includes a wire selection portion and a logic gate portion having transfer gates,

the logic gate portion has a programmable logic gate and a memory,

the wire selection portion has a wire switch and an input switch,

the wire switch is connected to the signal bus, the input switch, and the memory,

the input switch is connected to the signal bus and the programmable logic gate, and

the programmable logic gate is connected to the signal bus,

each of the wire switch and the input switch being controlled by a data signal stored in the memory.

18. A circuit as claimed in claim 17, wherein:

the memory comprises an SRAM, a DRAM, a ROM, an EPROM, and an EEPROM.

19. A circuit as claimed in claim 17, wherein:

the transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor.

20. A semiconductor integrated circuit device having a plurality of basic cells which are placed in a matrix form and are formed on a semiconductor substrate, wherein:

each of the basic cells includes a wire selection portion and a logic gate portion,

the logic gate portion has a MOS transistor,

the wire selection portion has a thin-film transistor serving as a transfer gate,

the wire selection portion being placed over the logic gate portion via an interlayer insulating film.

21. A device as claimed in claim 20, wherein:

the thin-film transistor comprises an n-channel enhancement type or an n-channel depletion type thin-film transistor.

22. A device as claimed in claim 20, wherein:

at least a pair of wiring patterns are formed in the interlayer insulating film, and

the thin-film transistor is placed between the wiring patterns.

23. A device as claimed in claim 20, wherein:

the thin-film transistor comprises any one of a lateral type and a vertical type.

24. A device as claimed in claim 20, wherein:

the thin-film transistor has at least a channel region, and

the channel region is formed by a non-doped polysilicon film.