Bias circuit for use with low-voltage power supply

• US 6,515,546 B2
• Filed: 06/06/2001
• Issued: 02/04/2003
• Est. Priority Date: 06/06/2001
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Anadigics Incorporated (Coherent Corp.)
• Inventors: Liwinski, Henry Z.
• Primary Examiner(s): Nguyen, Patricia T.
• Application Number:
  US09/875,117
• Publication Number:
  US 20020186084A1
• Time in Patent Office: 608 Days
• Field of Search: 330/296, 330/288, 330/290, 330/291
• US Class Current: 330/296
• CPC Class Codes: G05F 3/265 using bipolar transistors only
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 3/343 with semiconductor devices only

Abstract

A transistor bias circuit is provided that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains die mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit.

Claims

1. A circuit for biasing a first transistor having a control terminal, current-sink terminal, and current-source terminal and capable of operating from a power supply having positive and ground terminals, the circuit comprising:

a. a second transistor having a control terminal, current-sink terminal and current-source terminal,

i. wherein the control terminal of said second transistor is connected to the control terminal of such first transistor in a current-mirror configuration, and

ii. wherein the current-sink terminal of said second transistor is connected to the ground terminal of such power supply;

b. a first resistor connected between the current-source terminal of said second transistor and the positive terminal of such power supply;

c. a feedback circuit, including

i. a non-inverting amplifier having input and output ports,

(1) wherein the input port of said non-inverting amplifier is connected to the node formed by said first resistor and the current-source terminal of said second transistor; and

ii. a feedback transistor having a control terminal, current-sink terminal, and current-source terminal,

(1) wherein the control terminal of said feedback transistor is connected to the output port of said non-inverting amplifier,

(2) wherein the current-sink terminal of said feedback transistor is connected to the node formed by the connection of said second transistor to such first transistor, and

(3) wherein the current-source terminal of said feedback transistor is connected to the positive terminal of such power supply,

whereby said non-inverting amplifier increases the gain of the feedback circuit so that the bias circuit is relatively insensitive to fluctuations in supply voltage or temperature.

2. The circuit according to claim 1, wherein said second transistor is one of a BJT, an HBT, and a FET.

3. The circuit according to claim 1, wherein said feedback transistor is one of a BJT, an HBT, and a FET.

4. The circuit according to claim 1, further comprising a second resistor coupled between the current-sink terminal of said feedback transistor and the ground terminal of such power supply.

5. The circuit according to claim 1, further comprising:

a. a third resistor coupled between the control terminal of such first transistor and the current-sink terminal of said feedback transistor; and

b. a fourth resistor coupled between the control terminal of said second transistor and the current-sink terminal of said feedback transistor.

6. The circuit according to claim 1 wherein said non-inverting amplifier comprises two cascaded transistors, each having a control terminal, current-sink terminal, and current-source terminal.

7. The circuit according to claim 6, wherein said non-inverting amplifier further comprises:

a. two resistors, each coupled between the current-source terminal of one of said cascaded transistors, respectively, and the positive terminal of such power supply.

8. The circuit according to claim 7, wherein said non-inverting amplifier further comprises:

a. two resistors, each coupled between the current-sink terminal of one of said cascaded transistors, respectively, and the ground terminal of such power supply.

9. A method of biasing a first transistor having a control terminal, a current-sink terminal, and a current-source terminal and capable of operating from a power supply having positive and ground terminals via a bias circuit including a second transistor connected in a current-mirror configuration with the first transistor, the method comprising the steps of:

a. monitoring an electrical characteristic at the current-source terminal of the second transistor;

b. amplifying the monitored characteristic; and

c. feeding back the amplified characteristic to control the second transistor.

10. The method of claim 9, wherein the electrical characteristic is one of current and voltage.

11. The method of claim 9, wherein the step of amplifying comprises the steps of inverting the characteristic and then re-inverting the characteristic, such that a non-inverted amplified characteristic is produced.

12. The method of claim 9, further comprising the step of level-shifting the monitored characteristic.