Self-biased cascode RF power amplifier in sub-micron technical field

• US 6,515,547 B2
• Filed: 06/26/2001
• Issued: 02/04/2003
• Est. Priority Date: 06/26/2001
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Sowlati, Tirdad
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, KHANH V
• Application Number:
  US09/891,669
• Publication Number:
  US 20020196086A1
• Time in Patent Office: 588 Days
• Field of Search: 330/253, 330/277, 330/298, 330/302, 330/311
• US Class Current: 330/311
• CPC Class Codes: H03F 1/223 with MOSFET's

Abstract

A method for increasing the maximum useable supply voltage in an amplifier circuit is presented. A self-biased cascode amplifier circuit includes a first MOSFET and a second MOSFET connected in series and coupled between a DC voltage source terminal and a common terminal. An RF input signal terminal is coupled to a gate electrode of the first MOSFET, and the gate of the second MOSFET is connected between a resistor and a capacitor connected in series between the drain of the second MOSFET and the source of the first MOSFET. In preferred embodiments a unidirectionally-conducting boosting sub-circuit is coupled between a drain electrode and the gate electrode of the second MOSFET, which may comprise a diode-resistive sub-circuit, or a third MOSFET connected across a resistive voltage divider. The output of the amplifier circuit is taken from the drain electrode of the second MOSFET. These configuration permits the first and second MOSFETs to withstand a larger output voltage swing, thus permitting the use of a higher supply voltage and increased output power, without the necessity of complex biasing voltages.

Claims

1. A method of increasing a maximum useable supply voltage in a power amplifier circuit, comprising:

utilizing a cascode configuration; and

self-biasing said cascode configuration;

where the cascode configuration is self biased by;

coupling the gate of a common source transistor to a signal input, and

coupling the gate of an other transistor to its own drain;

where the gate of said other transistor is also capacitively coupled to ground;

where a unidirectionally-conducting sub circuit is coupled between the drain of said other transistor and said gate of said other transistor; and

where said unidirectionally-conductive sub circuit is a series connection of a resistor and one of a diode and a diode connected transistor.

2. The method of claim 1, where the gate of said other transistor is coupled to its drain via two resistors in series, with a third transistor connected such that it source is connected to the gate of said other transistor, its drain to the drain of said other transistor, and its gate between said two resistors in series.

3. A method of facilitating maximum signal swing in a cascode configuration amplifier circuit comprising:

connecting a signal input to the gate of a transistor of the cascode configuration amplifier circuit; and

self-biasing an other transistor such that its gate more closely follows the voltage of its drain on positive swing than on negative swing;

where the other transistor'"'"'s gate more closely follows the voltage of its drain on positive swing than on negative swing due to a resistor and a diode or a diode connected transistor being connected in series across the drain and gate of said other transistor.

4. An amplifier circuit, comprising a first MOSFET and a second MOSFET connected in series and coupled between a DC voltage source terminal and a common terminal, an RF input signal terminal being coupled to a gate electrode of said first MOSFET, and the gate of said second MOSFET connected between a first resistor and a capacitor connected in series between the drain of said second MOSFET and the source of said first MOSFET, where a series connection of a second resistor and one of a diode and a diode connected transistor are connected from the drain of said second MOSFET to the gate of said second MOSFET.

6. The amplifier circuit of any of claim 4 or 5, where a source electrode of said first MOSFET is connected to said common terminal by an inductor, and a drain electrode of said second MOSFET is coupled to said DC voltage source by an inductor.

7. The amplifier circuit of any of claim 4 or 5, where a gate electrode of said first MOSFET is coupled to said RF input signal terminal by a capacitor.

8. The amplifier circuit of any of claim 4 or 5, where the output of said amplifier circuit is coupled to a load by a matching circuit.

9. The amplifier circuit of any of claim 4 or 5, where said circuit is utilized twice as two sides of a differential amplifier circuit.

10. A differential amplifier of claim 9, used as a stage in a multistage amplifier.

5. An amplifier circuit, comprising a first MOSFET and a second MOSFET connected in series and coupled between a DC voltage source terminal and a common terminal, an RF input signal terminal being coupled to a gate electrode of said first MOSFET, and the gate of said second MOSFET connected between the series connection of a first resistor and a second resistor, and a capacitor, all connected in series between the drain of said second MOSFET and the source of said first MOSFET, where a third MOSFET is connected such that the drain of said third MOSFET is connected to the drain of said second MOSFET, the source of said third MOSFET is connected to the gate of said second MOSFET, and the gate of said third MOSFET is connected between the series connection of said first resistor and said second resistor.