Low cost three-dimensional memory array
First Claim
1. A 3-dimensional memory array comprising a plurality of vertically-stacked layers of memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached.
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Abstract
A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).
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Citations
75 Claims
- 1. A 3-dimensional memory array comprising a plurality of vertically-stacked layers of memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached.
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29. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory cells are arranged in a plurality of vertically-stacked layers of memory cells.
- 46. A memory array comprising a plurality of write-once, field programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein said memory cells are characterized by a read voltage no greater than 2 volts.
- 48. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein each memory cell comprises exactly two terminals.
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50. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory array comprises a plurality of wires comprising wordlines and bitlines, and wherein each memory cell is connected to exactly two wires:
- the respective wordline and the respective bitline.
- View Dependent Claims (51)
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52. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory cells comprise a semiconductor material and wherein the memory cells store digital media information selected from the group consisting of:
- digital text, digital books, digital music, digital audio, at least one digital still image, a sequence of digital images, digital video, at least one digital map, and combinations thereof.
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53. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory cells comprise one of the following:
- an organic polymer, a phase change material, and an amorphous solid.
- View Dependent Claims (54)
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55. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory array further comprises a substrate, and wherein the memory cells are fabricated above the substrate, and wherein the memory cells store digital media information selected from the group consisting of:
- digital text, digital books, digital music, digital audio, at least one digital still image, a sequence of digital images, digital video, at least one digital map, and combinations thereof.
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56. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory array further comprises a substrate, and wherein the memory cells are fabricated above the substrate, wherein the substrate comprises a semiconductor, and wherein the memory cells store digital media information selected from the group consisting of:
- digital text, digital books, digital music, digital audio, at least one digital still image, a sequence of digital images, digital video, at least one digital map, and combinations thereof.
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57. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory array further comprises a substrate, and wherein the memory cells are arranged on the substrate at a density no less than 3×
- 107 memory cells/mm2 of substrate area.
- View Dependent Claims (58)
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59. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein said memory cells are characterized by an average maximum read current density no greater than 1×
- 104 amperes/cm2.
- View Dependent Claims (60)
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61. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory cells store digital media information selected from the group consisting of:
- digital text, digital books, digital music, digital audio, at least one digital still image, a sequence of digital images, digital video, at least one digital map, and combinations thereof.
- View Dependent Claims (62, 63)
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64. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein the memory cells, when the respective antifuse layers are breached, are characterized by an average read current less than 6.3 microamperes;
- and wherein the memory cells, when the respective antifuse layers are intact, are characterized by an average read current less than the read current when the antifuse layer is breached.
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65. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein each cell comprises a programmed state, in which the read current is less than 6.3 microamperes, and another state, in which the read current is less than in the programmed state.
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66. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein each memory cell comprises a p-type semiconductor region characterized by a dopant concentration greater than 1×
- 1019/cm3.
- View Dependent Claims (67, 68)
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69. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein each memory cell comprises a p-type semiconductor doped with boron and characterized by a boron concentration greater than 1×
- 1019/cm3.
- View Dependent Claims (70, 71)
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72. A memory array comprising a plurality of write-once, field-programmable memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached, said memory cells storing digital media, wherein each memory cell further comprises first and second diode components, at least one of the diode components comprising a semiconductor region comprising a dopant at a concentration greater than 1×
- 1019/cm3.
- View Dependent Claims (73, 74, 75)
Specification