Method of anti-fuse repair

• US 6,515,931 B2
• Filed: 04/30/2001
• Issued: 02/04/2003
• Est. Priority Date: 08/20/1996
• Status: Expired due to Term

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W., Batra, Shubneesh
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/845,794
• Publication Number:
  US 20010026494A1
• Time in Patent Office: 645 Days
• Field of Search: 365/225.7, 365/189.01, 257/410, 257/530, 438/600
• US Class Current: 365/225.7
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit anti-fuse is described which is fabricated as a capacitor using a layer of oxide. The two plates of the anti-fuse are coupled to appropriate voltage levels to rupture the oxide and form a conductive short between the plates. One of the plates is formed as a diffused well which is coupled to an external voltage during programming. The well is biased to an internal voltage during normal operation of the circuit incorporating the anti-fuse.

Claims

1. An integrated circuit comprising:

a pin external to the integrated circuit;

a programming circuit; and

a plurality of anti-fuses coupled between the pin and the programming circuit, each anti-fuse comprising;

a first plate coupled to the pin to receive a predetermined voltage;

a second plate coupled to the programming circuit to receive a first programming voltage or a second programming voltage that is between the predetermined voltage and the first programming voltage; and

an insulator between the first plate and the second plate that is ruptured when the anti-fuse is programmed by the first programming voltage.

2. The integrated circuit of claim 1 wherein:

the first plate comprises an n-type well in a p-type silicon substrate, the n-type well having an n+-type well tie diffusion region that is coupled to the pin to receive the predetermined voltage;

the insulator comprises a layer of oxide; and

the second plate comprises a layer of n-type polysilicon.

3. The integrated circuit of claim 1 wherein:

the first plate comprises a p-type well in an n-type silicon substrate, the p-type well having a p+-type well tie diffusion that is coupled to the pin to receive the predetermined voltage;

the insulator comprises a layer of oxide; and

the second plate comprises a layer of p-type polysilicon.

4. The integrated circuit of claim 1 wherein:

the predetermined voltage comprises −

7 volts and the first programming voltage comprises +7 volts;

the integrated circuit comprises a memory device and further comprises a memory array, an address decoder including the anti-fuses, and input/output paths;

the programming circuit comprises a programming logic circuit; and

further comprising a bias network coupled to the well.

5. An integrated circuit comprising:

a pin external to the integrated circuit;

a programming circuit; and

a plurality of anti-fuses coupled between the pin and the programming circuit, each anti-fuse comprising;

a well of a first conductivity type in a substrate of a second conductivity type, the well being coupled to the pin to receive a predetermined voltage;

a plate coupled to the programming circuit to receive a first programming voltage or a second programming voltage that is between the predetermined voltage and the first programming voltage; and

an insulator between the well and the plate that is ruptured when the anti-fuse is programmed by the first programming voltage.

6. The integrated circuit of claim 5 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the insulator comprises a layer of oxide;

the plate comprises a layer of n-type polysilicon; and

further comprising an n+-type well tie diffusion region in the n-type well that is coupled to the pin to receive the predetermined voltage.

7. The integrated circuit of claim 5 wherein:

the substrate comprises an n-type silicon substrate;

the well comprises a p-type well in the substrate;

the insulator comprises a layer of oxide;

the plate comprises a layer of p-type polysilicon; and

further comprising a p+-type well tie diffusion region in the p-type well that is coupled to the pin to receive the predetermined voltage.

8. The integrated circuit of claim 5 wherein:

the predetermined voltage comprises −

7 volts and the first programming voltage comprises +7 volts;

the integrated circuit comprises a memory device and further comprises a memory array, an address decoder including the anti-fuses, and input/output paths;

the programming circuit comprises a programming logic circuit; and

further comprising a bias network coupled to the well.

9. An integrated circuit comprising:

a pin external to the integrated circuit;

a programming circuit; and

a plurality of anti-fuses coupled between the pin and the programming circuit, each anti-fuse comprising;

a plate coupled to the pin to receive a predetermined voltage;

a well of a first conductivity type in a substrate of a second conductivity type, the well being coupled to the programming circuit to receive a first programming voltage or a second programming voltage that is between the predetermined voltage and the first programming voltage; and

an insulator between the well and the plate that is ruptured when the anti-fuse is programmed by the first programming voltage.

10. The integrated circuit of claim 9 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the insulator comprises a layer of oxide;

the plate comprises a layer of n-type polysilicon; and

further comprising an n+-type well tie diffusion region in the n-type well that is coupled to the programming circuit.

11. The integrated circuit of claim 9 wherein:

the substrate comprises an n-type silicon substrate;

the well comprises a p-type well in the substrate;

the insulator comprises a layer of oxide;

the plate comprises a layer of p-type polysilicon; and

further comprising a p+-type well tie diffusion region in the p-type well that is coupled to the programming circuit.

12. The integrated circuit of claim 9, wherein:

the predetermined voltage comprises −

7 volts and the first programming voltage comprises +7 volts;

the integrated circuit comprises a memory device and further comprises a memory array, an address decoder including the anti-fuses, and input/output paths;

the programming circuit comprises a programming logic circuit; and

further comprising a bias network coupled to the plate.

13. An integrated circuit comprising:

a pin external to the integrated circuit;

a programming circuit; and

a plurality of anti-fuses coupled between the pin and the programming circuit, each anti-fuse comprising;

an n-type well in a p-type silicon substrate, the n-type well being coupled to the pin to receive a predetermined voltage;

a layer of n-type polysilicon coupled to the programming circuit to receive a first programming voltage or a second programming voltage that is between the predetermined voltage and the first programming voltage; and

an insulator between the n-type well and the layer of n-type polysilicon that is ruptured when the anti-fuse is programmed by the first programming voltage.

14. The integrated circuit of claim 13 wherein:

the insulator comprises a layer of oxide;

the predetermined voltage comprises −

7 volts and the first programming voltage comprises +7 volts;

the integrated circuit comprises a memory device and further comprises a memory array, an address decoder including the anti-fuses, and input/output paths;

the programming circuit comprises a programming logic circuit; and

further comprising;

a bias network coupled to the n-type well; and

an n+-type well tie diffusion region in the n-type well that is coupled to the pin to receive the predetermined voltage.

15. An integrated circuit comprising:

a pin external to the integrated circuit;

a programming circuit; and

a plurality of anti-fuses coupled between the pin and the programming circuit, each anti-fuse comprising;

a p-type well in an n-type silicon substrate, the p-type well being coupled to the pin to receive a predetermined voltage;

a layer of p-type polysilicon coupled to the programming circuit to receive a first programming voltage or a second programming voltage that is between the predetermined voltage and the first programming voltage; and

an insulator between the p-type well and the layer of p-type polysilicon that is ruptured when the anti-fuse is programmed by the first programming voltage.

16. The integrated circuit of claim 15 wherein:

the insulator comprises a layer of oxide;

the predetermined voltage comprises −

7 volts and the first programming voltage comprises +7 volts;

the integrated circuit comprises a memory device and further comprises a memory array, an address decoder including the anti-fuses, and input/output paths;

the programming circuit comprises a programming logic circuit; and

further comprising;

a bias network coupled to the p-type well; and

a p+-type well tie diffusion region in the p-type well that is coupled to the pin to receive the predetermined voltage.

17. A method comprising:

selecting a first group of anti-fuses in an integrated circuit to be programmed and a second group of anti-fuses in the integrated circuit that are not to be programmed, each anti-fuse in the first group and the second group comprising;

a first plate coupled to a pin external to the integrated circuit;

a second plate coupled to a programming circuit; and

an insulator between the first plate and the second plate;

coupling a predetermined voltage to the pin of the integrated circuit;

coupling a first programming voltage from the programming circuit to the second plate of each anti-fuse in the first group to rupture the insulator of each anti-fuse in the first group;

coupling a second programming voltage from the programming circuit to the second plate of each anti-fuse in the second group, the second programming voltage being between the predetermined voltage and the first programming voltage.

18. The method of claim 17 wherein:

coupling a predetermined voltage further comprises coupling the predetermined voltage to an n+-type well tie diffusion region in an n-type well in a p-type silicon substrate of each anti-fuse, each n+-type well tie diffusion region being coupled to the pin;

coupling a first programming voltage further comprises coupling the first programming voltage from the programming circuit to a layer of n-type polysilicon comprising the second plate of each anti-fuse in the first group to rupture a layer of oxide comprising the insulator of each anti-fuse in the first group; and

coupling a second programming voltage further comprises coupling the second programming voltage from the programming circuit to a layer of n-type polysilicon comprising the second plate of each anti-fuse in the second group to avoid rupture of a layer of oxide comprising the insulator of each anti-fuse in the second group.

19. The method of claim 17 wherein:

coupling a predetermined voltage further comprises coupling the predetermined voltage to a p+-type well tie diffusion region in a p-type well in an n-type silicon substrate of each anti-fuse, each p+-type well tie diffusion region being coupled to the pin;

coupling a first programming voltage further comprises coupling the first programming voltage from the programming circuit to a layer of p-type polysilicon comprising the second plate of each anti-fuse in the first group to rupture a layer of oxide comprising the insulator of each anti-fuse in the first group; and

coupling a second programming voltage further comprises coupling the second programming voltage from the programming circuit to a layer of p-type polysilicon comprising the second plate of each anti-fuse in the second group to avoid rupture of a layer of oxide comprising the insulator of each anti-fuse in the second group.

20. The method claim 17 wherein:

coupling a predetermined voltage further comprises coupling −

7 volts to the pin of the integrated circuit;

coupling a first programming voltage further comprises coupling +7 volts from a programming logic circuit comprising the programming circuit to the second plate of each anti-fuse in the first group; and

further comprising accessing a memory cell in a memory array of a memory device comprising the integrated circuit with an address coupled to an address decoder including the anti-fuses, and coupling a bit through input/output paths to the accessed memory cell to read or store the bit.

21. A method comprising:

selecting a first group of anti-fuses in an integrated circuit to be programmed and a second group of anti-fuses in the integrated circuit that are not to be programmed, each anti-fuse in the first group and the second group comprising;

a well of a first conductivity type in a substrate of a second conductivity type, the well being coupled to a pin external to the integrated circuit;

a plate coupled to a programming circuit; and

an insulator between the well and the plate;

coupling a predetermined voltage to the pin of the integrated circuit;

coupling a first programming voltage from the programing circuit to the plate of each anti-fuse in the first group to rupture the insulator of each anti-fuse in the first group;

coupling a second programming voltage from the programming circuit to the plate of each anti-fuse in the second group, the second programming voltage being between the predetermined voltage and the first programming voltage.

22. The method of claim 21 wherein:

coupling a predetermined voltage further comprises coupling the predetermined voltage to an n+-type well tie diffusion region in an n-type well in a p-type silicon substrate of each anti-fuse, each n+-type well tie diffusion region being coupled to the pin;

coupling a first programming voltage further comprises coupling the first programming voltage from the programming circuit to a layer of n-type polysilicon comprising the plate of each anti-fuse in the first group to rupture a layer of oxide comprising the insulator of each anti-fuse in the first group; and

coupling a second programming voltage further comprises coupling the second programming voltage from the programming circuit to a layer of n-type polysilicon comprising the plate of each anti-fuse in the second group to avoid rupture of a layer of oxide comprising the insulator of each anti-fuse in the second group.

23. The method of claim 21 wherein:

coupling a predetermined voltage further comprises coupling the predetermined voltage to a p+-type well tie diffusion region in a p-type well in an n-type silicon substrate of each anti-fuse, each p+-type well tie diffusion region being coupled to the pin;

coupling a first programming voltage further comprises coupling the first programming voltage from the programming circuit to a layer of p-type polysilicon comprising the plate of each anti-fuse in the first group to rupture a layer of oxide comprising the insulator of each anti-fuse in the first group; and

coupling a second programming voltage further comprises coupling the second programming voltage from the programming circuit to a layer of p-type polysilicon comprising the plate of each anti-fuse in the second group to avoid rupture of a layer of oxide comprising the insulator of each anti-fuse in the second group.

24. The method claim 21 wherein:

coupling a predetermined voltage further comprising coupling −

7 volts to the pin of the integrated circuit;

coupling a first programming voltage further comprises coupling +7 volts from a programming logic circuit comprising the programming circuit to the plate of each anti-fuse in the first group; and

further comprising accessing a memory cell in a memory array of a memory device comprising the integrated circuit with an address coupled to an address decoder including the anti-fuses, and coupling a bit through input/output paths to the accessed memory cell to read or store the bit.

25. A method comprising:

selecting a first group of anti-fuses in an integrated circuit to be programmed and a second group of anti-fuses in the integrated circuit that are not to be programmed, each anti-fuse in the first group and the second group comprising;

a plate coupled to a pin external to the integrated circuit;

a well of a first conductivity type in a substrate of a second conductivity type, the well being coupled to a programming circuit; and

an insulator between the well and the plate;

coupling a predetermined voltage to the pin of the integrated circuit;

coupling a first programming voltage from the programming circuit to the well of each anti-fuse in the first group to rupture the insulator of each anti-fuse in the first group;

coupling a second programming voltage from the programming circuit to the well of each anti-fuse in the second group, the second programming voltage being between the predetermined voltage and the first programming voltage.

26. The method of claim 25 wherein:

coupling a predetermined voltage further comprises coupling the predetermined voltage to a layer of n-type polysilicon comprising the plate of each anti-fuse, each layer of n-type polysilicon being coupled to the pin;

coupling a first programming voltage further comprises coupling the first programming voltage from the programming circuit to an n+-type well tie diffusion regon in an n-type well in a p-type silicon substrate of each anti-fuse in the first group to rupture a layer of oxide comprising the insulator of each anti-fuse in the first group; and

coupling a second programming voltage further comprises coupling the second programming voltage from the programming circuit to an n+-type well tie diffusion region in an n-type well in a p-type silicon substrate of each anti-fuse in the second group to avoid rupture of a layer of oxide comprising the insulator of each anti-fuse in the second group.

27. The method of claim 25 wherein:

coupling a predetermined voltage further comprises coupling the predetermined voltage to a layer of p-type polysilicon comprising the plate of each anti-fuse, each layer of p-type polysilicon being coupled to the pin;

coupling a first programming voltage further comprises coupling the first programming voltage from the programming circuit to a p+-type well tie diffusion region in a p-type well in an n-type silicon substrate of each anti-fuse in the first group to rupture a layer of oxide comprising the insulator of each anti-fuse in the first group; and

coupling a second programming voltage further comprises coupling the second programming voltage from the programming circuit to a p+-type well tie diffusion region in a p-type well in an n-type silicon substrate of each anti-fuse in the second group to avoid rupture of a layer of oxide comprising the insulator of each anti-fuse in the second group.

28. The method claim 25 wherein:

coupling a predetermined voltage further comprises coupling −

7 volts to the pin of the integrated circuit;

coupling a first programming voltage further comprising coupling +7 volts from a programming logic circuit comprising the programming circuit to the well of each anti-fuse in the first group; and

further comprising accessing a memory cell in a memory array of a memory device comprising the integrated circuit with an address coupled to an address decoder including the anti-fuses, and coupling a bit through input/output paths to the accessed memory cell to read or store the bit.

29. A method comprising:

selecting a first group of anti-fuses in an integrated circuit to be programmed and a second group of anti-fuses in the integrated circuit that are not to be programmed, each anti-fuse in the first group and the second group comprising;

an n-type well in a p-type silicon substrate, the n-type well being coupled to a pin external to the integrated circuit;

a layer of n-type polysilicon coupled to a programming circuit; and

an insulator between the n-type well and the layer of n-type polysilicon;

coupling a predetermined voltage to the pin of the integrated circuit;

coupling a first programming voltage from the programming circuit to the layer of n-type polysilicon of each anti-fuse in the first group to rupture the insulator of each anti-fuse in the first group; and

coupling a second programming voltage from the programming circuit to the layer of n-type polysilicon of each anti-fuse in the second group, the second programming voltage being between the predetermined voltage and the first programming voltage.

30. The method claim 29 wherein:

coupling a predetermined voltage further comprises coupling −

7 volts to the pin of the integrated circuit that is coupled to an n+-type well tie diffusion region in the n-type well of each anti-fuse;

coupling a first programming voltage further comprises coupling +7 volts from a programming logic circuit comprising the programming circuit to the layer of n-type polysilicon of each anti-fuse in the first group to rupture a layer of oxide comprising the insulator of each anti-fuse in the first group; and

further comprising accessing a memory cell in a memory array of a memory device comprising the integrated circuit with an address coupled to an address decoder including the anti-fuses, and coupling a bit through input/output paths to the accessed memory cell to read or store the bit.

31. A method comprising:

selecting a first group of anti-fuses in an integrated circuit to be programmed and a second group of anti-fuses in the integrated circuit that are not to be programmed, each anti-fuse in the first group and the second group comprising;

a p-type well in an n-type silicon substrate, the p-type well being coupled to a pin external to the integrated circuit;

a layer of p-type polysilicon coupled to a programming circuit; and

an insulator between the p-type well and the layer of p-type polysilicon;

coupling a predetermined voltage to the pin of the integrated circuit;

coupling a first programming voltage from the programming circuit to the layer of p-type polysilicon of each anti-fuse in the first group to rupture the insulator of each anti-fuse in the first group; and

coupling a second programming voltage from the programming circuit to the layer of p-type polysilicon of each anti-fuse in the second group, the second programming voltage being between the predetermined voltage and the first programming voltage.

32. The method of claim 31 wherein:

coupling a predetermined voltage further comprises coupling −

7 volts to the pin of the integrated circuit that is coupled to a p+-type well tie diffusion region in the p-type well of each anti-fuse;

coupling a first programming voltage further comprises coupling +7 volts from a programming logic circuit comprising the programming circuit to the layer of p-type polysilicon of each anti-fuse in the first group to rupture a layer of oxide comprising the insulator of each anti-fuse in the first group; and

further comprising accessing a memory cell in a memory array of a memory device comprising the integrated circuit with an address coupled to an address decoder including the anti-fuses, and coupling a bit through input/output paths to the accessed memory cell to read or store the bit.