AC scan diagnostic method

• US 6,516,432 B1
• Filed: 12/22/1999
• Issued: 02/04/2003
• Est. Priority Date: 12/22/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Song, Peilin, Druckerman, Howard B., Motika, Franco, Nigh, Phillip J.
• Primary Examiner(s): Ton, David
• Application Number:
  US09/469,699
• Time in Patent Office: 1,140 Days
• Field of Search: 714/727, 714/732, 714/733, 714/726, 714/728, 714/729, 714/731, 714/738, 714/744, 708/254, 712/227
• US Class Current: 714/732
• CPC Class Codes: G01R 31/318577 AC testing, e.g. current testing, burn-in

Abstract

Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and comparing the output against an expected result. The system comprises identification phase, verifications and localization, and a characterization phases. The system is adaptable for use with on-board diagnostics and is adaptable for use with on-product clock generation systems.

Claims

1. An apparatus for performing AC scan chain built-in self test and diagnostics of an integrated circuit, comprising:

a reconfigurable linear feedback shift register (LFSR) having an input and a plurality of output lines, the LFSR generating a bit pattern;

a plurality of scan chains having a plurality of latches, the scan chains interconnected to the LFSR, each scan chain serially receiving at a respective input the bit pattern output by the LFSR, and each scan chain propagating the bit pattern from the respective input to a respective output of each scan chain;

a multiple input signature register (MISR), the MISR receiving the bit patterns output by the respective scan chains;

the MISR generating a signature in accordance with the bit patterns input from the scan chains;

a comparison circuit for comparing the signature with an expected signature based upon the pattern input to the plurality of scan chains, wherein when the signature is equal to the expected signature, the scan chains are functioning correctly; and

a controller for reconfiguring the LFSR to vary the bit patterns output by the LFSR and for varying a timing sequence of operation of the LFSR, the plurality of scan chains, the MISR, and the comparison circuit.

2. The apparatus of claim 1 further comprising a plurality of serial data lines input to each of a respective scan chain latch for loading each scan chain latch independently of the LFSR.

3. The apparatus of claim 2 further comprising a plurality of multiplexers, the multiplexers selecting between one of the respective serial data lines and the output lines from the LFSR.

4. The apparatus of claim 3 wherein the scan chains are serially interconnected so that an output from one scan chain is applied to the input of a successive scan chain.

5. The apparatus of claim 4 wherein predetermined bit patterns are input to the respective scan chains in predetermined timing sets in accordance with control signals output by the controller.

6. The apparatus of claim 5 further comprising an on-board clock generator, the on-board clock generator receiving control signals from the controller and generating clock signals to effect a particular timing set in accordance with the control signals.

7. The apparatus of claim 6 wherein respective outputs of selected scan chains interconnect to the MISR in one of a serial and parallel manner, and wherein the comparison circuit compares the output of the MISR with an expected output determined in accordance with the input to the scan chains to identify a failing latch which works under some conditions but not all conditions.

8. An apparatus for performing AC scan chain built-in self test and diagnostics of an integrated circuit, comprising:

a reconfigurable linear feedback shift register (LFSR) having an input and a plurality of output lines, the LFSR generating a bit pattern;

a plurality of scan chains having a plurality of latches, the scan chains interconnected to the LFSR, each scan chain serially receiving at a respective input the bit pattern output by the LFSR, and each scan chain propagating the bit pattern from the respective input to a respective output of each scan chain;

a multiple input signature register (MISR), the MISR receiving the bit patterns output by the respective scan chains, the MISR generating a signature in accordance with the bit patterns input from the scan chains;

a comparison circuit for comparing the signature with an expected signature based upon the pattern input to the plurality of scan chains, wherein when the signature is equal to the expected signature, the scan chains are functioning correctly; and

an on-product clock generator (OPCG) to generate clock signals to synchronize operation of the LSFR, the plurality of scan chains, and the MISR.

9. The apparatus of claim 8 further comprising a logic built-in self test (LBIST) controller for controlling operation of the OPCG, the LSFR, the plurality of scan chains, and the MISR.

10. The apparatus of claim 8 further comprising a phase-lock-loop (PLL) circuit, the phase lock loop circuit generating a control signal to the OPCG to control operation of the OPCG.

11. The apparatus of claim 8 further comprising a phase-lock-loop (PLL) circuit, the phase lock loop circuit generating a control signal to the OPCG to control operation of the OPCG.

12. An apparatus for performing AC scan chain built-in self test and diagnostics of an integrated circuit, comprising:

a reconfigurable linear feedback shift register (LFSR) having an input and a plurality of output lines, the LFSR generating a bit pattern;

a plurality of scan chains having a plurality of latches, the scan chains interconnected to the LFSR, each scan chain serially receiving at a respective input the bit pattern output by the LFSR, and each scan chain propagating the bit pattern from the respective input to a respective output of each scan chain;

a multiple input signature register (MISR), the MISR receiving the bit patterns output by the respective scan chains, the MISR generating a signature in accordance with the bit patterns input from the scan chains;

a comparison circuit for comparing the signature with an expected signature based upon the pattern input to the plurality of scan chains, wherein when the signature is equal to the expected signature, the scan chains are functioning correctly;

an on-product clock generator (OPCG) to generate clock signals to synchronize operation of the LSFR, the plurality of scan chains, and the MISR; and

a logic built-in self test (LBIST) controller for controlling operation of the OPCG, the LSFR, the plurality of scan chains, and the MISR, wherein the LBIST varies generation of predetermined bit patterns input to the respective scan chains in predetermined timing sets.

13. The apparatus of claim 12 further comprising a plurality of serial data lines input to each of a respective scan chains loading each scan chain independently of the LFSR.

14. The apparatus of claim 12 further comprising a plurality of multiplexers, the multiplexers selecting between one of the respective serial data lines and the output lines from the LFSR.

15. The apparatus of claim 12 wherein the scan chain latches are serially interconnected so that an output from one scan chain latch is applied to the input of a successive scan chain latch.

16. The apparatus of claim 12 wherein the respective outputs of selected scan chains interconnect to the MISR in one of a serial and parallel manner, and wherein the comparison circuit compares the output of the MISR with an expected output determined in accordance with an the input to the scan chains to identify a failing latch which works under some conditions but not all conditions.