Design system for flip chip semiconductor device

• US 6,516,446 B2
• Filed: 04/27/2001
• Issued: 02/04/2003
• Est. Priority Date: 04/28/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Anzai, Takahiro
• Primary Examiner(s): Nguyen, Cuong Quang
• Application Number:
  US09/844,351
• Publication Number:
  US 20010039642A1
• Time in Patent Office: 648 Days
• Field of Search: 716/1-5
• US Class Current: 716/112
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A CAD system includes a storage device for storing information for the types and positions of cell blocks to be disposed in an internal circuit area, prohibition of arrangement of power source lines and electrode pads, and a plurality of layout parts each including an electrode pad and a connection cell. Each of the layout parts is selected based on the distance between the electrode pad and an associated I/O cell, thereby obviating the step of wiring between the electrode pad and the I/O cell.

Claims

1. A computer aided design (CAD) system for designing a layout of a flip chip semiconductor integrated circuit comprising:

a first storage section for storing first information including information for locations and types of circuit blocks in an internal circuit, and information for prohibition of arrangement of interconnect lines which depends on said type of said circuit block concerned;

a second storage section for storing second information including design rule information and information for prohibition of arrangement of electrode pads which depends on said types of said circuit block concerned;

a third storage section for storing third information including information for a plurality of layout parts to be arranged, each of said layout parts including an electrode pad and an associated connection cell having a specified length; and

a layout/wiring design section for performing design arrangement and wiring of at least one circuit block and a plurality of said layout parts in an internal circuit based on said first through third information.

2. The CAD system as defined in claim 1, wherein said layout/arrangement section designs for arrangement of said internal circuit based on said first information, arrangement of said electrode pads based on said second information, arrangement of interconnect lines between said internal circuit and said electrode pads based on said first and second information, and arrangement of said layout parts based on said third information.

3. The CAD system as defined in claim 2, further comprising a test section for testing a design obtained by said layout/wiring section based on at least a design rule for said internal circuit block.

4. The CAD system as defined in claim 1, wherein said first information includes chip size information.

5. The CAD system as defined in claim 1, wherein said layout/wiring section judges a macro block as one of said types of said internal circuit block, said judgement including whether or not said macro block operates on a power source different from a power source of another internal circuit block.

6. The CAD system as defined in claim 5, wherein said CAD system designs for arrangement of electrode pads for said macro block.

7. The CAD system as defined in claim 1, wherein each of said layout parts includes an electrode pad, a connection cell extending from said electrode pad, and a connection section formed at one of ends of said connection cell, said connection cells have different lengths, and a difference between said lengths of said connection cells corresponds to a pitch of said electrode pads to be arranged.

8. The CAD system as defined in claim 7, wherein said connection cell has an offset between a center of said connection cell and a center of said electrode pad, said offset being an integral multiple of a pitch of I/O cells.