Method for testing semiconductor memory devices, and apparatus and system for testing semiconductor memory devices

• US 6,518,073 B2
• Filed: 12/10/2001
• Issued: 02/11/2003
• Est. Priority Date: 01/25/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Momohara, Tomomi
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/988,834
• Publication Number:
  US 20020039799A1
• Time in Patent Office: 428 Days
• Field of Search: 438/4, 438/5, 438/10, 438/11, 438/12, 438/17, 438/18
• US Class Current: 438/4
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A method for testing a semiconductor device comprises executing a function test on the semiconductor device, executing a DC characteristic test on the semiconductor device, executing a remedy determination process of the semiconductor device, and executing a remedy process on the semiconductor device. The remedy determination process is performed in parallel to the DC test.

Claims

1. A method for testing a semiconductor device, comprising:

executing a first function test which detects an abnormal portion of a memory cell array of the semiconductor device;

executing a DC characteristic test which detects a DC characteristic of the semiconductor device, and executing a second function test different from the first function test;

checking a location of the abnormal portion of the memory cell array, based on abnormal portion with a spare portion, said arithmetic operation being performed in parallel to both the DC characteristic test and the second function test; and

executing a remedy process to program replacing data based on results of the arithmetic operation in a redundancy circuit of the semiconductor device.

2. The method according to claim 1, wherein said first function test, said DC characteristic test, said second function test, and said arithmetic operation are executed in parallel when a plurality of semiconductor devices formed on a wafer are tested.

3. The method according to claim 1, wherein said first function test, said DC characteristic test, said second function test, and said arithmetic operation are executed in parallel when all semiconductor devices formed on a wafer are tested.

4. The method according to claim 1, further comprising:

a determination process which determines whether or not the semiconductor device is a device that can be remedied,

said remedy process being executed for the device that can be remedied.

5. The method according to claim 4, wherein said determination process is performed by checking whether a number of defective addresses is larger than a predetermined limit number.

6. A method for testing a semiconductor device, comprising:

executing a first function test which detects an abnormal portion of a memory cell array of the semiconductor device;

executing a DC characteristic test which detects a DC characteristic of the semiconductor device, and executing a second function test different from the first function test;

checking a location of the abnormal portion of the memory cell array, based on results of the first function test, and performing an arithmetic operation to replace the abnormal portion with a spare portion, said arithmetic operation being performed in parallel to both the DC characteristic test and the second function test;

executing a remedy process to program replacing data based on results of the arithmetic operation in a redundancy circuit of the semiconductor device; and

executing a final function test on the semiconductor device being programmed with the replacing data.

7. The method according to claim 6, wherein said first function test, said DC characteristic test, said second function test, and said arithmetic operation are executed in parallel when a plurality of semiconductor devices formed on a wafer are tested.

8. The method according to claim 6, wherein said first function test, said DC characteristic test, said second function test, and said arithmetic operation are executed in parallel when all semiconductor devices formed on a wafer are tested.

9. The method according to claim 6, further comprising:

a determination process which determines whether or not the semiconductor device is a device that can be remedied,

said remedy process being executed for the device that can be remedied.

10. The method according to claim 9, wherein said determination process is performed by checking whether a number of defective addresses is larger than a predetermined limit number.

11. A method for testing a semiconductor device, comprising:

executing a function test required for remedy determination on the semiconductor of device;

executing a DC characteristic test and remaining function test on the semiconductor device;

executing a remedy determination process of the semiconductor device, said remedy determination process being performed in parallel to both the DC characteristic test and the remaining function test; and

executing a remedy process on the semiconductor device.

12. The method according to claim 11, wherein said remedy determination process executes at a tester.

13. The method according to claim 11, wherein said remedy process is executed by a tester.

14. The method according to claim 11, wherein said function test, said DC characteristic test, and a remedy determination process are executed in parallel when a plurality of semiconductor devices formed on a wafer are tested.

15. The method according to claim 11, wherein said function test, said DC characteristic test, said remaining function test, and said remedy determination process are executed in parallel when all semiconductor devices formed on a wafer are tested.

16. The method according to claim 11, wherein said remedy determination process includes determining whether or not the semiconductor device is a device that can be remedied,

said remedy process being executed for the device that can be remedied.

17. The method according to claim 16, wherein said remedy determination process is performed by checking whether a number of defective addresses is larger than a predetermined limit number.

24. The method according to claim 13, wherein said remedy determination process is performed by checking whether a number of defective addresses is larger than a predetermined limit number.

18. A method for testing a semiconductor device, comprising:

executing a function test on the semiconductor device;

executing a DC characteristic test on the semiconductor device;

executing a remedy determination process of the semiconductor device, said remedy determination process being performed in parallel to the DC characteristic test; and

executing a remedy process on the semiconductor device.

19. The method according to claim 18, wherein said remedy determination process executes at a tester.

20. The method according to claim 18, wherein said remedy process is executed by a tester.

21. The method according to claim 18, wherein said function test, said DC characteristic test, and said remedy determination process are executed in parallel when a plurality of semiconductor devices formed on a wafer are tested.

22. The method according to claim 18, wherein said function test, said DC characteristic test, and a remedy determination process are executed in parallel when all semiconductor devices formed on a wafer are tested.

23. The method according to claim 18, wherein said remedy determination process includes determining whether or not the semiconductor device is a device that can be remedied,

said remedy process being executed for the device that can be remedied.