Semiconductor device and method for manufacturing

• US 6,518,092 B2
• Filed: 02/28/2001
• Issued: 02/11/2003
• Est. Priority Date: 07/13/2000
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Kikuchi, Hidekazu
• Primary Examiner(s): Graybill, David E.
• Application Number:
  US09/794,108
• Publication Number:
  US 20020005568A1
• Time in Patent Office: 713 Days
• Field of Search: 438/665, 438/964, 438/107, 438/108, 438/110, 438/113, 438/114, 438/126, 438/613, 438/614
• US Class Current: 438/107
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device which has trenches for raising the reliability thereof and a method for manufacturing such device. An electrode pad, and a protective film and an interlayer film which comprise an opening on top of this electrode pad, are formed on a substrate. A rewiring pattern which is in contact with the electrode pad at this opening is formed on top of the interlayer film. In addition, a trench is formed, by means of etching, in the region on this interlayer film where said rewiring pattern is not formed. A bump is formed on top of said rewiring pattern. The rewiring pattern and the trench are covered by means of a sealing film. The sealing film exposes the upper end of the bump. An external terminal is formed on the upper end of this bump. The trenches make the contact area between the covering film and the sealing film larger and therefore increase the adhesion between the covering film and the sealing film. The rougher the surface of the trench the better the adhesion between the covering film and the sealing film. Improving the adhesion makes it difficult for the sealing film to become detached so that the semiconductor device becomes more reliable.

Claims

1. A method for manufacturing a semiconductor device comprising steps of:

forming an electrode pad and an integrated circuit on top of a substrate;

forming, on top of said substrate, a covering film which comprises an opening on top of said electrode pad;

forming, on top of said covering film, a rewiring pattern which is in contact with said electrode pad at said opening;

forming in a region of said covering film beneath which said integrated circuit is formed and said rewiring pattern is not formed, a trench that does not expose the integrated circuit;

forming a bump on top of said rewiring pattern; and

forming a sealing film which covers said rewiring pattern and said trench, in such a way that said sealing film exposes the upper end of said bump.

2. The method for manufacturing a semiconductor device according to claim 1, wherein said step of forming a covering film comprises steps of:

forming, on top of said substrate, a protective film which comprises a first opening on top of said electrode pad; and

forming, on top of said protective film, an interlayer film which comprises a second opening on top of said electrode pad.

3. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of forming, on the surface of said interlayer film, a modifying layer for improving the adhesion of the interlayer film with respect to said rewiring pattern.

4. The method for manufacturing a semiconductor device according to claim 3 wherein said step of forming a modifying layer comprises a step of performing plasma processing on the surface of said interlayer film.

5. The method for manufacturing a semiconductor device according to claim 1, wherein said step of forming a rewiring pattern comprises steps of:

forming an metallic thin film for improving the adhesion of this rewiring pattern with respect to said covering film, and

forming metallic wiring on the surface of said metallic thin film.

6. The method for manufacturing a semiconductor device according to claim 3, wherein said modifying layer is segmented at each rewiring pattern by means of said step of forming a trench.

7. The method for manufacturing a semiconductor device according to claim 1, wherein said step of forming a trench comprises a wet etching process.

8. The method for manufacturing a semiconductor device according to claim 1, wherein said step of forming a trench comprises an anisotropic etching process.

9. The method for manufacturing a semiconductor device according to claim 8, wherein said anisotropic etching is plasma etching.

10. The method for manufacturing a semiconductor device according to claim 2, wherein said step of forming a trench is the same step as a step of providing a second opening in said interlayer film.

11. The method for manufacturing a semiconductor device according to claim 2, wherein said step of forming a trench is a step of forming a trench with a depth which causes said protective film to be exposed.

12. The method for manufacturing a semiconductor device according to claim 2, wherein the first opening of the protective film has a side face, and wherein said step of forming an interlayer film includes a step of forming said second opening so that said side face is exposed.

13. The method for manufacturing a semiconductor device according to claim 1 further comprising a step of forming an external terminal on top of said bump.

14. The method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor device is manufactured by means of a wafer level chip size package method.

15. A method for manufacturing a semiconductor device comprising steps of:

forming an electrode pad and an integrated circuit on a substrate;

forming a covering film that covers the integrated circuit and has an opening that exposes the electrode pad;

forming a rewiring pattern on a covering region of the covering film that excludes a trench region of the covering film, the wiring pattern contacting the electrode pad at the opening;

forming a trench in the trench region of the covering film;

forming a bump on the rewiring pattern; and

forming a sealing film that covers the rewiring pattern and the trench, such that the sealing film exposes an upper end of the bump.

16. The method for manufacturing a semiconductor device according to claim 15, wherein said step of forming a covering film comprises steps of:

forming on the substrate a protective film, the protective film having a first opening exposing the electrode pad, and

forming on top of said protective film, an interlayer film having a second directly over the first opening so as to expose the electrode pad.

17. The method for manufacturing a semiconductor device according to claim 16, further comprising the step of forming, on the surface of said interlayer film, a modifying layer that increases adhesion of the interlayer film with respect to the rewiring pattern.

18. The method for manufacturing a semiconductor device according to claim 17, wherein said step of forming a modifying layer comprises performing plasma processing on the surface of the interlayer film.

19. The method for manufacturing a semiconductor device according to claim 15, wherein said step of forming a rewiring pattern comprises steps of:

forming over the covering film a metallic thin film that increases adhesion of the rewiring pattern with respect to the covering film, and

forming metallic wiring on the surface of said metallic thin film.

20. The method for manufacturing a semiconductor device according to claim 16, wherein said step of forming a trench exposes the protective film.

21. The method for manufacturing a semiconductor device according to claim 16, wherein the first opening has a side face, and wherein said step of forming an interlayer film includes forming the second opening so that the side face is exposed.

22. A method for manufacturing a semiconductor device comprising steps of:

forming an electrode pad and an integrated circuit on a substrate;

forming a protective film over the integrated circuit with a first opening that exposes the electrode pad,

forming, an interlayer film over the protective film, with a second opening directly over the first opening so as to expose the electrode pad;

forming a modifying layer over the interlayer film;

forming a rewiring pattern on the modifying layer so as to cover a covering region of the interlayer film that excludes a trench region of the interlayer film, the wiring pattern contacting the electrode pad at the first opening, the modifying layer increasing the adhesion of the interlayer film with respect to the rewiring pattern;

forming a trench in the trench region of the interlayer film;

forming a bump in contact with an upper surface of the rewiring pattern; and

forming a sealing film that covers the rewiring pattern and the trench, such that the sealing film exposes an upper end of the bump.

23. The method for manufacturing a semiconductor device according to claim 22, wherein said step of forming a trench includes removing a portion of the modifying layer over the trench region.

24. A method for manufacturing a semiconductor device comprising steps of:

providing a semiconductor substrate having an integrated circuit on a surface thereof;

forming an electrode pad on the substrate surface in contact with the integrated circuit;

forming an insulating layer on the substrate surface so as to expose the electrode pad, the insulating layer having a first region that includes a vicinity of the exposed electrode pad, and having a second region that excludes the first region;

forming a conductive layer on the exposed electrode pad, the conductive layer covering the insulating layer only in the first region;

removing a surface portion of the insulating layer in the second region; and

forming a resin layer over the first and second regions of the insulating layer and the conductive layer.

25. A method for manufacturing a semiconductor device comprising steps of:

forming an electrode pad on top of a substrate;

forming, on top of said substrate, a covering film which comprises an opening on top of said electrode pad;

forming, on top of said covering film, a rewiring pattern which is in contact with said electrode pad at said opening;

forming a trench in a region of said covering film over which said rewiring pattern is not formed, said trench being separated from said opening by a portion of said covering film;

forming a bump on top of said rewiring pattern; and

forming a sealing film which covers said rewiring pattern and said trench, in such a way that said sealing film exposes the upper end of said bump.

26. A method for manufacturing a semiconductor device comprising steps of:

forming an electrode pad on top of a substrate;

forming, on top of said substrate, a covering film which comprises an opening on top of said electrode pad;

forming, on top of said covering film, a rewiring pattern which is in contact with said electrode pad at said opening;

after said step of forming the rewiring pattern, removing a portion of the covering film from a region of the covering film, spaced from the covering film opening, over which the rewiring pattern is not formed, thereby to form a trench in the covering film region, the trench being spaced from the opening;

forming a bump on top of said rewiring pattern; and

forming a sealing film which covers said rewiring pattern and the trench, in such a way that said sealing film exposes the upper end of said bump.