Structure and process for buried bitline and single sided buried conductor formation

• US 6,518,118 B2
• Filed: 03/15/2001
• Issued: 02/11/2003
• Est. Priority Date: 03/15/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Athavale, Satish D., Divakaruni, Ramachandra, Mandelman, Jack A.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/808,799
• Publication Number:
  US 20020130346A1
• Time in Patent Office: 698 Days
• Field of Search: 257/68, 257/301, 257/302, 438/243, 438/244, 438/245, 438/246, 438/248, 438/386, 438/387, 438/388, 438/389, 438/391
• US Class Current: 438/243
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

Semiconductor devices generally, and in particular DRAM memory devices, having buried, single-sided conductors are provided. Additionally, methods of fabricating semiconductor devices having buried, single-sided conductors are provided.

Claims

1. A method for formation of a trench capacitor cell having a single-sided buried conductor comprising:

providing a semiconductor substrate successively layered with first pad SiN, hardened oxide, and second pad SiN and having a trench etched therein;

providing trench liner about an interior wall of said trench, said liner comprising a first SiN liner, an oxide liner and a second SiN liner, said second SiN liner being outermost relative to said first SiN liner and said oxide liner being between said first and second SiN liners;

filling the trench with trench dielectric;

pulling back said second pad SiN;

conformally layering polysilicon over said second pad SiN;

performing angled boron implantation into a portion of said conformal polysilicon on one side of said trench, wherein the implantation divides said trench into first and second sides;

etching undoped polysilicon from above said first side of said trench;

etching said dielectric from said first side of said trench to expose said first SiN liner;

etching exposed first SiN liner from said first side of said trench;

forming and recessing a buried bitline conductor layer in said first side of said trench;

etching further exposed oxide liner and first SiN liner from said first side of said trench to form space for a polysilicon strap;

forming a polysilicon strap in said space;

forming trench top oxide over said polysilicon strap;

etching exposed said second SiN liner from said first side of said trench to expose semiconductor surface;

growing gate oxide on exposed semiconductor surface;

forming gate conductor layer adjacent to said gate oxide;

forming a dielectric layer over said gate conductor;

depositing a blanket of SiN over said dielectric layer; and

depositing a blanket of BSG.

2. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein filling said trench comprises:

filling said trench with trench dielectric;

planarizing said trench;

recessing said oxide to a depth at or below the interface between said second layer of SiN and the hardened oxide.

3. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1 wherein said trench dielectric is selected from the group consisting of HDP oxide, BSG, BPSG, or other suitable dielectric.

4. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein forming a buried bitline conductor layer comprises:

depositing a layer of buried bitline conductor;

planarizing said buried bitline layer to height of said hardened oxide layer; and

recessing said buried bitline layer.

5. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein said buried bitline conductor is selected from the group consisting of Ti, TiN, polysilicon and doped polysilicon.

6. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein forming gate conductor comprises:

depositing a layer of gate conductor material;

planarizing said gate conductor layer to lower surface of said hardened oxide layer; and

recessing said gate conductor layer.

7. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein said gate conductor material comprises conductive substances selected from the group consisting of intrinsic or doped polysilicon, W/WSi_x, and W/WN.

8. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein forming dielectric layer comprises:

layer depositing a layer of dielectric oxide;

planarizing said dielectric oxide layer to top of said hardened oxide layer; and

recessing said gate oxide layer.