Structure and process for buried bitline and single sided buried conductor formation
First Claim
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1. A method for formation of a trench capacitor cell having a single-sided buried conductor comprising:
- providing a semiconductor substrate successively layered with first pad SiN, hardened oxide, and second pad SiN and having a trench etched therein;
providing trench liner about an interior wall of said trench, said liner comprising a first SiN liner, an oxide liner and a second SiN liner, said second SiN liner being outermost relative to said first SiN liner and said oxide liner being between said first and second SiN liners;
filling the trench with trench dielectric;
pulling back said second pad SiN;
conformally layering polysilicon over said second pad SiN;
performing angled boron implantation into a portion of said conformal polysilicon on one side of said trench, wherein the implantation divides said trench into first and second sides;
etching undoped polysilicon from above said first side of said trench;
etching said dielectric from said first side of said trench to expose said first SiN liner;
etching exposed first SiN liner from said first side of said trench;
forming and recessing a buried bitline conductor layer in said first side of said trench;
etching further exposed oxide liner and first SiN liner from said first side of said trench to form space for a polysilicon strap;
forming a polysilicon strap in said space;
forming trench top oxide over said polysilicon strap;
etching exposed said second SiN liner from said first side of said trench to expose semiconductor surface;
growing gate oxide on exposed semiconductor surface;
forming gate conductor layer adjacent to said gate oxide;
forming a dielectric layer over said gate conductor;
depositing a blanket of SiN over said dielectric layer; and
depositing a blanket of BSG.
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Abstract
Semiconductor devices generally, and in particular DRAM memory devices, having buried, single-sided conductors are provided. Additionally, methods of fabricating semiconductor devices having buried, single-sided conductors are provided.
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Citations
8 Claims
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1. A method for formation of a trench capacitor cell having a single-sided buried conductor comprising:
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providing a semiconductor substrate successively layered with first pad SiN, hardened oxide, and second pad SiN and having a trench etched therein;
providing trench liner about an interior wall of said trench, said liner comprising a first SiN liner, an oxide liner and a second SiN liner, said second SiN liner being outermost relative to said first SiN liner and said oxide liner being between said first and second SiN liners;
filling the trench with trench dielectric;
pulling back said second pad SiN;
conformally layering polysilicon over said second pad SiN;
performing angled boron implantation into a portion of said conformal polysilicon on one side of said trench, wherein the implantation divides said trench into first and second sides;
etching undoped polysilicon from above said first side of said trench;
etching said dielectric from said first side of said trench to expose said first SiN liner;
etching exposed first SiN liner from said first side of said trench;
forming and recessing a buried bitline conductor layer in said first side of said trench;
etching further exposed oxide liner and first SiN liner from said first side of said trench to form space for a polysilicon strap;
forming a polysilicon strap in said space;
forming trench top oxide over said polysilicon strap;
etching exposed said second SiN liner from said first side of said trench to expose semiconductor surface;
growing gate oxide on exposed semiconductor surface;
forming gate conductor layer adjacent to said gate oxide;
forming a dielectric layer over said gate conductor;
depositing a blanket of SiN over said dielectric layer; and
depositing a blanket of BSG. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
filling said trench with trench dielectric;
planarizing said trench;
recessing said oxide to a depth at or below the interface between said second layer of SiN and the hardened oxide.
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3. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1 wherein said trench dielectric is selected from the group consisting of HDP oxide, BSG, BPSG, or other suitable dielectric.
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4. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein forming a buried bitline conductor layer comprises:
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depositing a layer of buried bitline conductor;
planarizing said buried bitline layer to height of said hardened oxide layer; and
recessing said buried bitline layer.
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5. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein said buried bitline conductor is selected from the group consisting of Ti, TiN, polysilicon and doped polysilicon.
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6. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein forming gate conductor comprises:
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depositing a layer of gate conductor material;
planarizing said gate conductor layer to lower surface of said hardened oxide layer; and
recessing said gate conductor layer.
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7. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein said gate conductor material comprises conductive substances selected from the group consisting of intrinsic or doped polysilicon, W/WSix, and W/WN.
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8. A method for formation of a trench capacitor cell having a single-sided buried conductor, according to claim 1, wherein forming dielectric layer comprises:
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layer depositing a layer of dielectric oxide;
planarizing said dielectric oxide layer to top of said hardened oxide layer; and
recessing said gate oxide layer.
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Specification