Method of forming and operating trench split gate non-volatile flash memory cell structure

• US 6,518,126 B2
• Filed: 04/23/2002
• Issued: 02/11/2003
• Est. Priority Date: 04/24/2001
• Status: Expired due to Fees

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Fu-Yuan, King, Ya-Chin, Lee, Kung-Hong, Chou, Hsin-Fen, Hsu, Ching-Hsiang, Wu, Meng-Yi, Yang, Ching-Song
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US10/063,435
• Publication Number:
  US 20020175394A1
• Time in Patent Office: 294 Days
• Field of Search: 382/58, 382/59, 382/66, 382/67, 382/70, 385/89
• US Class Current: 438/259
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.

Claims

1. A method of forming a trench split-gate non-volatile flash memory cell structure, comprising the steps of:

forming a P-type substrate;

forming a deep N-well layer over the P-type substrate;

forming a shallow P-well layer over the deep N-well layer;

forming a gate region above the shallow P-well layer and marking out a drain region and an auxiliary gate region on each side of the gate region;

forming a spacer on each side of the gate region;

forming a trench in the deep N-well layer and the shallow P-well layer within the auxiliary gate region;

forming an oxide layer inside the trench;

performing a heavy dopant implantation to implant ions into the deep N-well layer and the drain region of the shallow P-well layer underneath the trench, thereby forming a source terminal and a drain terminal;

depositing polysilicon material to fill the trench, thereby forming a trench auxiliary gate;

forming a first polysilicon layer over the gate region, thereby forming a floating gate;

forming an isolation layer over the first polysilicon layer, the drain region and the filled trench region; and

forming a second polysilicon layer over the isolation layer, thereby forming a control gate.

2. The method of claim 1, wherein material forming the spacers and the isolation layer includes an oxide-nitride of silicon.

3. The method of claim 1, wherein material forming the spacers and the isolation layer includes an oxide-nitride-oxide of silicon.

4. The method of claim 1, wherein material forming the spacers and the isolation layer includes silicon nitride.

5. The method of claim 1, wherein after the step of depositing polysilicon material into the trench, further includes forming a silicon nitride layer over the exposed surface of the drain region and the polysilicon layer.