Trench MOSFET with double-diffused body profile

• US 6,518,128 B2
• Filed: 06/14/2001
• Issued: 02/11/2003
• Est. Priority Date: 06/16/2000
• Status: Expired due to Fees

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US09/881,253
• Publication Number:
  US 20020009854A1
• Time in Patent Office: 607 Days
• Field of Search: 438/268, 438/270, 438/589, 438/212, 438/272, 438/283
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions. Each trench body region and each termination body region has a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region, and the second region being disposed above the first region and adjacent and extending to an outer wall of one of said plurality of trenches. A plurality of source regions of the first conductivity type are positioned adjacent the trenches within upper portions the trench.

Claims

1. A method of forming a trench MOSFET device comprising:

providing a substrate of a first conductivity type;

forming an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;

forming a plurality of trenches within said epitaxial layer, said trenches being lined by a first insulating layer and containing a conductive region adjacent to the first insulating layer;

forming within an upper portion of said epitaxial layer one or more trench body regions and one or more termination body regions, said termination body regions extending into said epitaxial layer to a greater depth than said trench body regions;

each trench body region and each termination body region comprising (a) a first region of a second conductivity type, said second conductivity type being opposite said first conductivity type, and (b) a second region of said second conductivity type adjacent said first region, said second region having a greater majority carrier concentration than said first region, and said second region being disposed above said first region and adjacent and extending to an outer wall of one of said plurality of trenches; and

forming a plurality of source regions of said first conductivity type adjacent said trenches within upper portions said trench body regions.

6. The method of claim 1, wherein the step of forming said trenches includes the step of forming a patterned masking layer over the epitaxial layer and etching said trenches through said masking layer.

7. The method of claim 1, wherein said first insulating layer is an oxide layer.

8. The method of claim 7, wherein the step of forming the oxide layer comprises providing an oxide layer via dry oxidation.

9. The method of claim 1, wherein the conductive region is a polycrystalline silicon region.

10. The method of claim 9, wherein the step of providing a conductive region within said trenches comprises depositing a layer of polycrystalline silicon and subsequently etching the polycrystalline silicon layer.

15. The method of claim 1, wherein the step of forming the source regions comprises forming a patterned masking layer and implanting and diffusing a dopant into upper portions of the trench body regions.

2. A method of forming a trench MOSFET device comprising:

providing a substrate of a first conductivity type;

forming an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;

forming a plurality of trenches within said epitaxial layer, said trenches being lined by a first insulating layer and containing a conductive region adjacent to the first insulating layer;

forming within an upper portion of said epitaxial layer one or more trench body regions and one or more termination body regions, said termination body regions extending into said epitaxial layer to a greater depth than said trench body regions;

each trench body region and each termination body region comprising (a) a first region of a second conductivity type, said second conductivity type being opposite said first conductivity type, and (b) a second region of said second conductivity type adjacent said first region, said second region having a greater majority carrier concentration than said first region, and said second region being disposed above said first region; and

forming a plurality of source regions of said first conductivity type adjacent said trenches within upper portions said trench body regions,

 

wherein said step of forming said one or more trench body regions and said one or more termination body regions comprises;

forming a terminal masking feature;

forming a layer of second conductivity type within an upper portion of said epitaxial layer;

forming said trenches in said epitaxial layer, said trenches extending through said layer of second conductivity type such that distinct first regions of second conductivity type are formed;

forming an oxide layer over at least portions of trench walls adjacent said first regions, said step of forming said oxide layer resulting in areas of reduced majority carrier concentration within said first regions adjacent said oxide layer; and

forming second regions of second conductivity type within said epitaxial layer adjacent to and above said first regions of second conductivity type;

wherein said trenches are spaced sufficiently close such that, during the step of forming the oxide layer, the majority concentration is reduced throughout said first regions between said trenches; and

wherein said terminal masking feature is spaced sufficiently far from a nearest peripheral trench such that the step of forming the oxide layer has substantially no effect on bulk majority carrier concentration in said first regions between said peripheral trench and said masking feature.

3. The method of claim 2, wherein said MOSFET device is a silicon device.

4. The method of claim 3, wherein the maximum distance between said trenches ranges from 1.2 to 2.0 microns and wherein the minimum distance between said peripheral trenches and said terminal oxide feature ranges from 3.0 to 4.0 microns.

5. The method of claim 2, wherein said step of forming said layer of second conductivity type and the step of forming said second regions include implanting and diffusing a dopant into the epitaxial layer.

11. The method of claim 3, wherein the step forming an oxide layer over at least portions of said trench walls adjacent said first regions comprises dry oxidation at a temperature ranging from 900 to 1100°

C.

12. The method of claim 11, wherein the temperature ranges from 900 to 950°

C.

13. The method of claim 3, wherein the step of forming an oxide layer over at least portions of said trench walls adjacent said first regions of second conductivity type comprises oxidation in steam at a temperature ranging from 900 to 1100°

C.

14. The method of claim 13, wherein the temperature ranges from 900 to 950°

C.

16. The method of claim 3, wherein said first conductivity type is N-type conductivity, wherein said second conductivity type is P-type conductivity, and wherein said body regions are doped with boron.