Semiconductor device having trenches and process for same

• US 6,518,144 B2
• Filed: 03/22/2001
• Issued: 02/11/2003
• Est. Priority Date: 10/10/2000
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nitta, Tetsuya, Minato, Tadaharu
• Primary Examiner(s): Graybill, David E.
• Application Number:
  US09/813,791
• Publication Number:
  US 20020040994A1
• Time in Patent Office: 691 Days
• Field of Search: 438/700, 438/701, 438/435, 438/424, 438/425, 438/431, 438/437, 148/DIG.50
• US Class Current: 438/424
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

The elements and the trenches are arranged alternately, in repetition, on the main surface of a semiconductor substrate, each of the plurality of elements arranged alternately, in repetition, with the trenches has a configuration (for example, STM) which operates in the same operational mode, and an insulating layer, which is filled into the trenches, and doesn'"'"'t have a void at a position (the position shallower than the broken line L) shallower than the pn junction to which the largest electric field in the element is applied. Thereby, a semiconductor device and a process for the same, where voids inside of the trenches can be reduced and the film thickness of the insulating film, for filling in the trenches which remain on the surface of the semiconductor substrate, can be made thinner, can be gained through a simple method.

Claims

1. A process for a semiconductor device having a trench including:

the step of forming a trench in a main surface of a semiconductor substrate;

the step of forming a first insulating film on the main surface of said semiconductor substrate in one step, or in a plurality of divided steps, so as to fill in said trench and to have a void in said trench;

the step of forming an aperture which reaches to the inside of said trench in said first insulating film by connecting said void with the outside of said trench through an anisotropic etching in said first insulating film so that the upper edge corner parts of said aperture in said first insulating film have a more round edge than the upper edge corner parts of said trench and of reducing the film thickness of said first insulating film on the main surface of said semiconductor substrate; and

the step of forming a second insulating film on the main surface of said semiconductor substrate in one step, or in a plurality of divided steps, so as to fill in said aperture.

2. The process for a semiconductor device having a trench according to claim 1, wherein said step of forming said first insulating film, said step of etching anisotropically said first insulating film and said step of forming said second insulating film are repeated, twice, or more, in this order.

3. The process for a semiconductor device having a trench according to claim 1, wherein said first and said second insulating films are any of a silicon oxide film, a silicon nitride film or a complex film of a silicon oxide film and a silicon nitride film, formed through a chemical vapor deposition method.

4. The process for a semiconductor device having a trench according to claim 3, wherein before the completion of the filling in of said trench with said first insulating film or before completion of filling in of said trench with said second insulating film, sintering treatment is carried out in order that the insulating film within said trench is made higher in density, physically or stoichiometrically, so as to reduce the stress and that the stress occurrence due to the thermal treatments in the following steps is suppressed.

5. The process for a semiconductor device having a trench according to claim 4, wherein said sintering treatment is carried out at a temperature of 800°

C., or higher, and under a water vapor atmosphere, a burning oxidization atmosphere or an atmosphere of a high partial pressure of oxygen.

6. The process for a semiconductor device having a trench according to claim 4, wherein the temperature in said sintering treatment is higher than in any other temperatures in the following steps.

7. The process for a semiconductor device having a trench according to claim 1, wherein the aspect ratio of said trench is at least 10.

8. The process for a semiconductor device having a trench according to claim 1, wherein the anisotropic etching of said first insulating film incompletely removes the first insulating film from the main surface of said semiconductor substrate.