Semiconductor device structure and method for forming

• US 6,518,146 B1
• Filed: 01/09/2002
• Issued: 02/11/2003
• Est. Priority Date: 01/09/2002
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Ingersoll, Paul A., Singh, Rana P.
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US10/045,863
• Time in Patent Office: 398 Days
• Field of Search: 438/427, 438/425, 438/426, 438/424, 257/510, 257/513
• US Class Current: 438/427
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Abstract

A semiconductor device has both a logic section and a non-volatile memory (NVM) section. Transistors in both sections are separated by trench isolation. The logic isolation has narrower trenches than NVM trenches and both types of trenches have corners at the tops thereof. The trenches are lined by growing an oxide that is necessarily to take care of the plasma damage of the substrate, which is preferably silicon, that occurs during the formation of the trenches. These oxide liners are grown to a greater thickness in the NVM trenches than in the logic trenches to obtain a greater degree of corner rounding in the NVM trenches. This growth differential is achieved by selectively implanting the NVM trenches with a species that speeds oxide growth or selectively implanting the logic trenches with a species that retards oxide growth. As a further alternative, the NVM trenches can be implanted with a growth enhancing species and the logic trenches with a retarding species.

Claims

1. A method for forming a semiconductor device structure in a semiconductor layer, comprising:

forming a first trench of a first width and a first corner and forming a second trench of a second width and a second corner, the first width differing from the second width;

forming a mask overlying the second trench;

creating a modifying layer that modifies oxidation rate of exposed portions of the semiconductor device structure not covered by the mask;

removing the mask; and

thermally growing an insulating layer on the semiconductor structure to form an insulated first trench and an insulated second trench.

2. The method of claim 1 wherein the thermally growing of the insulating layer modifies the first corner to have a radius of curvature that is substantially greater than the second corner.

3. The method of claim 1 wherein the creating of the modifying layer further comprises one of implanting a species that modifies oxidation rate or depositing a species that modifies oxidation rate.

4. The method of claim 3 further comprising implementing the species as a member of the halide family of elements.

5. The method of claim 1 wherein the creating of the modifying layer that modifies oxidation rate further comprises:

implanting a species that enhances oxidation.

6. The method of claim 1 wherein the creating of the modifying layer that modifies oxidation rate further comprises:

implanting a species that retards oxidation.

7. The method of claim 6 further comprising implanting the species that retards oxidation as nitrogen.

8. The method of claim 1 further comprising:

forming the first trench within a memory portion of the semiconductor device structure and forming the second trench within a logic circuitry portion of the semiconductor device structure.

9. The method of claim 1 further comprising:

thermally growing the insulating layer as an oxide layer.

10. The method of claim 1 further comprising:

thermally growing the insulating layer to grow a trench oxide liner that is thicker in the first trench than in the second trench.

11. The method of claim 1 further comprising:

forming a barrier layer and a stress relief layer over the semiconductor layer in areas adjacent to the first trench and the second trench, the barrier layer and the stress relief layer inhibiting the thermally growing of the insulating layer and the implanting of the species that modifies oxidation rate.

12. A semiconductor device structure formed in a semiconductor layer, comprising:

a first trench of a first width and a first corner;

a second trench of a second width that differs from the first width, the second trench having a second corner; and

a grown insulator in the first trench and in the second trench;

wherein the first corner has a first radius of curvature that is substantially larger than a second radius of curvature of the second corner; and

wherein the grown insulator in the first trench comprises a material that enhances oxidation rate within the first trench as compared to oxidation rate within the second trench.

13. The semiconductor device of claim 12 further comprising:

a pad nitride and a pad oxide adjacent to the first trench and the second trench.

14. A semiconductor device structure formed in a semiconductor layer, comprising:

a first trench of a first width and a first corner;

a second trench of a second width that differs from the first width, the second trench having a second corner; and

a grown insulator in the first trench and in the second trench;

wherein the first corner has a first radius of curvature that is substantially larger than a second radius of curvature of the second corner; and

wherein the grown insulator in the second trench comprises a material that retards oxidation rate within the second trench as compared to oxidation rate within the first trench.

15. A method for forming a semiconductor device structure in a semiconductor layer, comprising:

forming a first trench of a first width in the semiconductor layer;

forming a second trench of a second width in the semiconductor layer; and

substantially simultaneously forming an insulating layer within the first trench and the second trench by using different oxidation rates in the first trench and the second trench and

wherein forming the first trench and forming the second trench further comprise implementing the first width and the second width as substantially equal widths.

16. A method for forming a semiconductor device structure in a semiconductor layer, comprising:

forming a first trench of a first width in the semiconductor layer;

forming a second trench of a second width in the semiconductor layer; and

substantially simultaneously forming an insulating layer within the first trench and the second trench by using different oxidation rates in the first trench and the second trench;

wherein forming an insulating layer within the first trench and the second trench by using different oxidation rates further comprises implanting a species in the first trench that enhances oxidation.

20. The method of claim 16 further comprising:

identifying an area of an integrated circuit containing the semiconductor device that requires high reliability and implementing the first trench in the area.

21. The method of claim 16 further comprising:

forming the first trench having a corner with a radius of curvature that is substantially greater than a radius of curvature of a corner of the second trench.

17. A method for forming a semiconductor device structure in a semiconductor layer, comprising:

forming a first trench of a first width in the semiconductor layer;

forming a second trench of a second width in the semiconductor layer; and

substantially simultaneously forming an insulating layer within the first trench and the second trench by using different oxidation rates in the first trench and the second trench;

wherein forming an insulating layer within the first trench and the second trench by using different oxidation rates further comprises implanting a species in the first trench that retards oxidation.

18. A method for forming a semiconductor device structure in a semiconductor layer, comprising:

forming a first trench of a first width in the semiconductor layer;

forming a second trench of a second width in the semiconductor layer; and

substantially simultaneously forming an insulating layer within the first trench and the second trench by using different oxidation rates in the first trench and the second trench;

wherein forming an insulating layer within the first trench and the second trench by using different oxidation rates further comprises implanting a species in the first trench that enhances oxidation and implanting a species in the second trench that retards oxidation.

19. A method for forming a semiconductor device structure in a semiconductor layer, comprising:

forming a first trench of a first width in the semiconductor layer;

forming a second trench of a second width in the semiconductor layer; and

substantially simultaneously forming an insulating layer within the first trench and the second trench by using different oxidation rates in the first trench and the second trench;

wherein forming an insulating layer within the first trench and the second trench by using different oxidation rates further comprises selectively depositing a predetermined material in the second trench that retards oxidation.