Method for manufacturing a semiconductor device having a metal layer floating over a substrate

• US 6,518,165 B1
• Filed: 02/22/2001
• Issued: 02/11/2003
• Est. Priority Date: 07/28/1998
• Status: Expired due to Fees

• Current Assignee: Korea Advanced Institute of Science and Technology
• Original Assignee: Korea Advanced Institute of Science and Technology
• Inventors: Yoon, Eui Sik, Kim, Choong Ki, Yoon, Jun Bo, Han, Chul Hi
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/763,401
• Time in Patent Office: 719 Days
• Field of Search: 438/52-53, 438/619, 438/622-624
• US Class Current: 438/619
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing a semiconductor device where a passive element, such as, an inductor, is floating over a substrate, where an integrated circuit is formed, such that the overall area of the semiconductor device may be highly reduced. According to the present invention, a first metal layer is formed on the substrate, a first masking layer is formed on a portion of the first metal layer, a second metal layer is formed on other portion of the first metal layer on which the first masking layer is not formed, and a second masking layer is formed on the first masking layer and the second metal layer. Then, the first masking layer and a portion of the second masking layer which includes a portion which covers the first masking layer is removed, a third metal layer is formed on portions of the first and second metal layers which are exposed by the step of removing the first masking layer and the portion of the second masking layer. Finally, the second masking layer, the second metal layer; and the first metal layer except a portion which the third metal layer covers are removed. In this way, the area for integrating various passive elements can be saved and the overall area for the semiconductor device including the integrated circuit and the passive elements may be reduced.

Claims

1. A method for manufacturing a semiconductor device having a substrate 101 and a metal layer floating over the substrate 101, the method comprising the steps of:

forming a first metal layer 203 on the substrate 101;

forming a second metal layer 205 on a portion of said first metal layer 203 such that side surfaces of said second metal layer 205 and an upper surface of other portion of said first metal layer 203 on which said second metal layer 205 is not formed define a recess;

forming a third metal layer 102 on said first and second metal layers 203 and 205 such that a portion of said third metal layer 102 is located on a predetermined portion of said second metal layer 205 and other portion of said third metal layer 102 fills said recess;

removing said second metal layer 205; and

removing a portion of said first metal layer 203 which is not covered by said third metal layer 102.

2. The method of claim 1 further comprising the steps of:

forming integrated circuits on the substrate 101; and

forming a protective layer on said circuits, before said step of forming said first metal layer 203

wherein said step of forming the first metal layer 203 forms said first metal layer 203 on said protective layer and a portion of said substrate 101 which is not covered by said protective layer.

3. The method of claim 1, wherein said step of forming the first metal layer 203 forms the first metal layer 203 on the substrate 101 by using vapor-deposition.

4. The method of claim 1, wherein said step of forming the second metal layer 205 is performed by plating the second metal layer 205 on said other portion of the first metal layer 203 using said first metal layer 203 as a seed metal for the plating.

5. The method of claim 1, wherein said step of forming the third metal layer 102 is performed by plating the third metal layer 102 on said portions of the second metal layer 205 using said second metal layer 205 as a seed metal for the plating.

6. The method of claim 1, wherein said step of removing said second metal layer 205 selectively removes said second metal layer 205 by using a selective etchant which etches only the second metal layer 205 between the second and third metal layers 205 and 102.

7. The method of claim 1, further comprising the steps of:

forming a fourth metal layer on a portion of said third metal layer 102 such that side surfaces of said fourth metal layer and an upper surface of other portion of said third metal layer 102 on which said fourth metal layer is not formed define a second recess;

forming a fifth metal layer on said third and fourth metal layers such that a portion of said fifth metal layer is located on a predetermined portion of said fourth metal layer and other portion of said fifth metal layer fills said second recess; and

removing said fourth metal layer.

8. A method for manufacturing a semiconductor device having a substrate 101 and a metal layer floating over the substrate 101, the method comprising the steps of:

forming a first metal layer 203 on the substrate 101;

forming a first masking layer 204 on a portion of said first metal layer 203;

forming a second metal layer 205 on other portion of said first metal layer 203 on which said first masking layer 204 is not formed;

forming a second masking layer 206 on said first masking layer 204 and said second metal layer 205;

removing said first masking layer 204 and a portion of said second masking layer 206 which includes a portion which covers said first masking layer 204;

forming a third metal layer 102 on portions of said first and second metal layers 203 and 205 which are exposed by said step of removing said first masking layer 204 and the portion of said second masking layer 206;

removing said second masking layer 206;

removing said second metal layer 205; and

removing a portion of said first metal layer 203 which is not covered by said third metal layer 102.

9. The method of claim 8 further comprising the steps of:

forming integrated circuits on the substrate 101; and

forming a protective layer on said circuits, before said step of forming said first metal layer 203,

wherein said step of forming the first metal layer 203 forms said first metal layer 203 on said protective layer and a portion of said substrate 101 which is not covered by said protective layer.

10. The method of claim 9, wherein said step of forming the first masking layer 204 forms said first masking layer 204 on a portion of said first metal layer 203 which is formed on said portion of the substrate 101 which is not covered by said protective layer.

11. The method of claim 8, wherein said step of forming the first metal layer 203 forms the first metal layer 203 on the substrate 101 by using vapor-deposition.

12. The method of claim 8, wherein said step of forming the second metal layer 205 is performed by plating the second metal layer 205 on said other portion of the first metal layer 203 using said first metal layer 203 as a seed metal for the plating.

13. The method of claim 8, wherein said step of forming the third metal layer 102 is performed by plating the third metal layer 102 on said portions of the second metal layer 205 using said second metal layer 205 as a seed metal for the plating.

14. The method of claim 8, wherein said step of removing said second metal layer 205 selectively removes said second metal layer 205 by using a selective etchant which etches only the second metal layer 205 between the second and third metal layers 205 and 102.

15. The method of claim 8, wherein said second and third metal layers 205 and 102 are made of nickel and copper, respectively.

16. The method of claim 8, wherein said second and third metal layers 205 and 102 are made of copper and nickel, respectively.

17. The method of claim 8 further comprising the steps of:

irradiating said first masking layer 204, after said step of forming the first masking layer 204; and

irradiating said portion of said second masking layer 206, before said step of removing said first masking layer 204 and the portion of said second masking layer 206, and

wherein said step of removing said first masking layer 204 and the portion of said second masking layer 206 removes said irradiated first masking layer 204 and said irradiated portion of said second masking layer 206 by development.

18. The method of claim 17, wherein said steps of irradiating use ultraviolet radiation.

19. The method of claim 8, further comprising the steps of:

forming a third masking layer 204 on a portion of said third metal layer 102, after said step of removing the second masking layer 206;

forming a fourth metal layer 205 on other portion of said third metal layer 102203 on which said third masking layer 204 is not formed;

forming a fourth masking layer 206 on said third masking layer 204 and said fourth metal layer 205;

removing said third masking layer and a portion of said fourth masking layer which includes a portion which covers said third masking layer;

forming a fifth metal layer on portions of said third and fourth metal layers which are exposed by said step of removing said third masking layer and a portion of said fourth masking layer;

removing said fourth masking layer; and

removing said fourth metal layer.

20. A method for manufacturing a semiconductor device having a substrate 101 and a metal layer floating over the substrate 101, the method comprising the steps of:

forming a first metal layer 203 on the substrate 101;

forming a first masking layer 204 on a portion of said first metal layer 203;

forming a second metal layer 205 on other portion of said first metal layer 203 on which said first masking layer 204 is not formed;

removing said first masking layer 204 to expose side surfaces of said second metal layer 205 and a surface of said portion of said first metal layer 203, such that the exposed surfaces define a recess;

forming a third metal layer 102 on said first and second metal layers 203 and 205 such that said recess is filled with said third metal layer 102;

removing a portion of said third metal layer 102 such that the portion which fills said recess is remained;

forming a second masking layer 206 on said second and third metal layers 205 and 102;

removing a portion of said second masking layer 206 which includes a portion which covers said third metal layer 102;

forming a metal layer 102 on portions of said second and third metal layers 205 and 102 which are exposed by said step of removing the portion of said second masking layer 206;

removing said second masking layer 204;

removing said second metal layer 205; and

removing a portion of said first metal layer 203 which is not covered by said third metal layer 102.

21. The method of claim 20 further comprising the steps of:

forming integrated circuits on the substrate 101; and

forming a protective layer on said circuits, before said step of forming said first metal layer 203,

wherein said step of forming the first metal layer 203 forms said first metal layer 203 on said protective layer and a portion of said substrate 101 which is not covered by said protective layer.

22. The method of claim 21, wherein said step of forming the first masking layer 204 forms said first masking layer 204 on a portion of said first metal layer 203 which is formed on said portion of the substrate 101 which is not covered by said protective layer.

23. The method of claim 20, wherein said step of forming the first metal layer 203 forms the first metal layer 203 on the substrate 101 by using vapor-deposition.

24. The method of claim 20, wherein said step of forming the second metal layer 205 is performed by plating the second metal layer 205 on said other portion of the first metal layer 203 using said first metal layer 203 as a seed metal for the plating.

25. The method of claim 20, wherein said step of forming the third metal layer 102 is performed by plating the third metal layer 102 on said portions of the second metal layer 205 using said second metal layer 205 as a seed metal for the plating.

26. The method of claim 20, wherein said step of removing said second metal layer 205 selectively removes said second metal layer 205 by using a selective etchant which etches only the second metal layer 205 between the second and third metal layers 205 and 102.

27. The method of claim 20, wherein said second and third metal layers 205 and 102 are made of nickel and copper, respectively.

28. The method of claim 20, wherein said second and third metal layers 205 and 102 are made of copper and nickel, respectively.

29. The method of claim 20 further comprising the step of irradiating said portion of said second masking layer 206 with ultraviolet radiation, before said step of removing the portion of said second masking layer 206, and

wherein said step of removing the portion of said second masking layer 206 removes said irradiated portion of said second masking layer 206 by development.