Liquid phase deposition of a silicon oxide layer for use as a liner on the surface of a dual damascene opening in a low dielectric constant layer

• US 6,518,166 B1
• Filed: 04/23/2001
• Issued: 02/11/2003
• Est. Priority Date: 04/23/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Frank, Chen, Sheng Hsiung, Chen, Shun Long, Shih, Tsu, Lin, Hungtse
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): YEVSIKOV, VICTOR V
• Application Number:
  US09/839,700
• Time in Patent Office: 659 Days
• Field of Search: 438/706, 438/590, 438/723, 438/724, 438/622-623, 438/638, 438/627, 438/637, 438/618
• US Class Current: 438/622
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02131 the material being halogen doped silicon oxides, e.g. FSG
• CPC Class Codes: H01L 21/02134 the material comprising hydrogen silsesquioxane, e.g. HSQ
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/316 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

A process for forming a dual damascene opening, in a composite layer comprised with low k layers, to accommodate a dual damascene type, copper structure, has been developed. The process features the use of a silicon oxide layer, formed on the surfaces of the composite layer, exposed in the narrow diameter, via hole component of the dual damascene opening. The silicon oxide layer prevents via poisoning, or outgassing of amines or hydroxyls from the low k layers exposed in the via hole opening, that can evolve during a subsequent photolithographic development cycle, used to define the trench shape component of the dual damascene opening. The protective silicon oxide layer is conformally formed on the exposed-surfaces of the via hole component, via a liquid phase deposition procedure, performed at room temperature.

Claims

1. A method of forming a dual damascene opening in low dielectric constant (low k) layers, on a semiconductor substrate, comprising the steps of:

providing a lower level metal interconnect structure;

forming a composite insulator layer on said lower level metal interconnect structure, comprised of an underlying low k layer, a stop layer, and an overlying low k layer;

forming a via opening in said composite insulator layer;

performing a liquid phase deposition procedure to form an undoped silicon oxide layer on the sides of said via opening;

forming a trench in said overlying low k layer, wherein said via opening is located below said trench, and with said via opening now comprised with liquid phase deposited undoped silicon oxide spacer; and

forming a metal structure in said trench and in said via opening, with a metal via structure located in said via opening, contacting said underlying lower level metal interconnect structure.

2. The method of claim 1, wherein said underlying low k layer is comprised of hydrogen silsesquioxane (HSQ), applied at a thickness between about 3000 to 3000 Angstroms, via spin on procedures, and comprised with a dielectric constant between about 2.8 to 3.0.

3. The method of claim 1, where said stop layer is a silicon nitride layer, comprised with a thickness between about 50 to 500 Angstroms.

4. The method of claim 1, wherein said overlying low k layer is comprised of hydrogen silsesquioxane (HSQ), applied at a thickness between about 3000 to 30000 Angstroms, via spin on procedures, and comprised with a dielectric constant between about 2.8 to 3.0.

5. The method of claim 1, wherein said via opening is formed via an anisotropic RIE procedure using CHF₃ as an etchant for said underlying low k layer, while using CF₄ or Cl₂ as an etchant for said stop layer.

6. The method of claim 1, wherein the diameter of said via opening is between about 100 to 10000 Angstroms.

7. The method of claim 1, wherein said silicon oxide layer is obtained via a liquid phase deposition procedure, performed at room temperature in a solution of H₂SiF₆, titrating H₃BO₃ to precipitate silicon oxide.

8. The method of claim 1, wherein said silicon oxide layer is formed via liquid phase deposition procedures at a thickness between about 20 to 200 Angstroms.

9. The method of claim 1, wherein said trench is formed via a selective RIE procedure, using CHF₃ as an etchant for said overlying low k layer.

10. The method of claim 1, wherein the etch rate ratio of said overlying low k layer, to said stop layer, using CHF₃ as an etchant, is between about 10 to 20, to 1.

11. The method of claim 1, wherein said metal structure is copper structure.

12. A method of forming a dual damascene opening in low dielectric constant (low k), layers, comprising the steps of:

providing a lower level metal interconnect structure;

applying a first low k layer;

depositing a silicon nitride layer;

depositing a second low k layer;

performing a first dry etch procedure to form a via opening with a narrow diameter, between about 100 to 10,000 Angstroms, in said second low k layer, in said silicon nitride layer, and in said first low k layer, exposing a portion of the top surface of said lower level metal interconnect structure;

performing a liquid phase deposition procedure to form an undoped silicon oxide layer, between about 20 to 200 Angstroms, conformal with the inner surface of said via opening;

performing a second dry etch procedure to form a trench in said second low k layer, and in said silicon nitride layer, wherein said via opening is located below said trench, and with the diameter of said trench larger than the diameter of said via opening, and with liquid phase deposition, undoped silicon oxide spacers, formed on sides of said via opening; and

forming a copper structure in said via opening and in said trench, with a copper via structure located in said via opening, overlying and contacting said lower level metal interconnect structure.

13. The method of claim 12, wherein said first low k layer is comprised of hydrogen silsesquioxane (HSQ), applied at a thickness between about 3000 to 30000 Angstroms, via spin on procedures, and comprised with a dielectric constant between about 2.8 to 3.0.

14. The method of claim 12, where said silicon nitride layer is obtained via PECVD procedures, to a thickness between about 50 to 500 Angstroms.

15. The method of claim 12, wherein said second low k layer is comprised of hydrogen silsesquioxane (HSQ), applied at a thickness between about 3000 to 30000 Angstroms, via spin on procedures, and comprised with a dielectric constant between about 2.8 to 3.0.

16. The method of claim 12, wherein said first dry etching procedure is an anisotropic RIE procedure, performed using CHF₃ as an etchant for said second, and for said first low k layer, while using CF₄ or Cl₂ as an etchant for said silicon nitride layer.

17. The method of claim 12, wherein said liquid phase deposition procedure is performed at room temperature, and carried out in a solution of H₂SiF₆, titrating H₃BO₃ to precipitate said silicon oxide layer.

18. The method of claim 12, wherein said second dry etch procedure is a selective RIE procedure, using CHF₃ as an etchant for said low k layer.

19. The method of claim 12, wherein the etch rate ratio of said second low k layer, to said silicon nitride layer, using CHF₃ as an etchant, is between about 10 to 20, to 1.