Analog-to-digital converter with multiplexed input channels

• US 6,518,909 B1
• Filed: 09/25/2001
• Issued: 02/11/2003
• Est. Priority Date: 03/30/2001
• Status: Expired due to Term

• Current Assignee: Pixim, Inc. (Sony Group Corp.)
• Original Assignee: Pixim, Inc. (Sony Group Corp.)
• Inventors: Bidermann, William R., Yang, David Xiao Dong
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US09/965,600
• Time in Patent Office: 504 Days
• Field of Search: 341/155, 341/169, 341/170, 341/159, 341/161, 341/152
• US Class Current: 341/155
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp

Abstract

A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Claims

1. A circuit comprising:

an analog-to-digital (A/D) converter for converting each of a plurality of analog input signals to a digital value, comprising;

a comparator having a first input terminal coupled to receive a first signal having a plurality of levels, a second input terminal coupled to receive said plurality of analog input signals, and a third input terminal for receiving an input select signal, said comparator including a multiplexer coupling said plurality of analog input signals to a plurality of corresponding input signal paths, said multiplexer selecting one of said plurality of input signal paths based on said input select signal; and

a latch having a first input terminal coupled to receive an output signal of said comparator, said latch having a data input terminal coupled to receive a series of binary signals, an output signal of said comparator controlling when said latch provides an output signal corresponding to a binary signal applied to said data input terminal;

wherein said comparator comparing said first signal with a selected one of said plurality of analog input signals to generate said output signal, and said latch provides at least a portion of an N-bit code representing said selected one of said plurality of analog input signals applied to said second input terminal of said comparator.

2. The circuit of claim 1, wherein said N-bit digital code is a Gray code.

3. The circuit of claim 1, further comprising:

a first signal generator generating a series of binary codes representing analog levels, said first signal generator comprising a digital-to-analog converter connected to receive said binary codes and to generate said first signal being connected to said first input terminal of said comparator.

4. The circuit of claim 1, wherein said first signal is an analog ramped signal for each bit of said N-bit digital code.

5. The circuit of claim 1, further comprising:

a binary signal generator for generating said series of binary signals.

6. The circuit of claim 1, wherein said input select signal comprises a plurality of input select bits, each of said plurality of input select bits being coupled to select one of said plurality of analog input signals.

7. The circuit of claim 6, wherein said comparator comprises:

a differential pair comprising;

a first transistor having a control terminal coupled to receive said first signal, a first current handling terminal coupled to a current mirror, and a second current handling terminal coupled to a current source, said first current handling terminal of said first transistor being an output terminal of said differential pair;

a first node coupling said plurality of input signal paths to said current mirror, each of said plurality of input signal paths including a second transistor and a third transistor connected in series between said first node and said current source, said second transistor having a control terminal coupled to a respective one of said input select bits, and said third transistor having a control terminal coupled to a respective one of said plurality of analog input signals;

wherein said input select bits selectively enable one of said plurality of input signal paths; and

an inverter having an input terminal coupled to said output terminal of said differential pair and generating said output signal of said comparator.

8. The circuit of claim 7, wherein said differential pair of said comparator further comprises a fourth transistor coupled between said current mirror and said first current handling terminal of said first transistor, said fourth transistor having a control terminal coupled to a first reference voltage turning said fourth transistor on, a first current handling terminal of said fourth transistor being said output terminal of said differential pair.

9. The circuit of claim 8, wherein said first reference voltage is a positive power supply voltage VDD of said circuit.

10. The circuit of claim 7, wherein said comparator further comprises:

a plurality of reset transistors, each of said reset transistors having a control terminal coupled to receive a reset signal, a first current handling terminal coupled to said first node, and a second current handling terminal coupled to said control terminal of said third transistor of a respective one of said plurality of input signal paths.

11. The circuit of claim 10, wherein said reset signal comprises a plurality of reset signals, and each of said control terminal of said reset transistors is coupled to a respective one of said plurality of reset signals.

12. The circuit of claim 7, wherein said current source comprises a fifth transistor having a control terminal coupled to a bias voltage, a first current handling terminal coupled to said second current handling terminal of said first transistor and providing a reference current, and a second current handling terminal coupled to a second reference voltage.

13. The circuit of claim 12, wherein said second reference voltage is a ground voltage.

14. The circuit of claim 7, wherein said current mirror comprises a sixth transistor and a seventh transistor, gate terminals of said sixth and seventh transistors being connected together and to a first current handling terminal of said seventh transistor, said first current handling terminal of said seventh transistor also coupled to said first current handling terminal of said first transistor, a first current handling terminal of said sixth transistor being coupled to said first node, and second current handling terminals of said sixth and seventh transistors being coupled to a first reference voltage.

15. The circuit of claim 1, further comprising:

an image sensor formed as an integrated circuit having a plurality of photodetectors, said photodetectors formed within an image sensor array, each of said photodetectors generating an analog signal, said comparator and said latch being formed within said image sensor array proximate to said photodetectors for converting an analog signal generated by at least one photodetector into a digital code,

wherein said comparator is one of a plurality of comparators and said latch is one of a plurality of latches all formed within said image sensor array as part of a plurality of analog-to-digital converters.

16. The circuit of claim 15 wherein one comparator and one latch are associated with a group of photodetectors, each of said photodetectors generating one of said plurality of analog input signals.

17. The circuit of claim 1 further comprising:

an image sensor formed as an integrated circuit having a plurality of photodetectors, each of said photodetectors generating an analog signal, said photodetectors being formed with an image sensor array, and wherein said A/D