High sensitive data signal amplifying circuit

• US 6,519,196 B1
• Filed: 11/28/2000
• Issued: 02/11/2003
• Est. Priority Date: 11/30/1999
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Lee, Jae-Jin, Jang, Ji-Eun
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/722,476
• Time in Patent Office: 805 Days
• Field of Search: 365/205, 365/207, 365/208, 365/190, 327/51
• US Class Current: 365/205
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

A high sensitive data signal amplifying circuit is capable of amplifying data signals having a small differential voltage by amplifying the data signals transferred from bit line amplifying unit in two stages. The high sensitive data signal amplifying circuit includes: a bit line amplifying unit for amplifying data stored at a memory cell and loading the amplified data on one of a bit line and a bit bar line; a column address selecting unit for transferring an output signal of the bit line amplifying unit depending on a column address signal; a first data signal amplifying unit for amplifying a data signal transferred by the column address selecting unit; a second data signal amplifying unit for amplifying an output signal from the first data signal amplifying unit; and a data signal transferring unit for transferring an output signal of the second data signal amplifying unit to output to a buffering unit.

Claims

1. A high sensitive data signal amplifying circuit comprising:

bit line amplifying means for amplifying data stored at a memory cell and loading the amplified data on one of a bit line and a bit bar line;

column address selecting means for transferring an output signal of the bit line amplifying means depending on a column address signal;

first data signal amplifying means for amplifying a data signal transferred by the column address selecting means, wherein the first data signal amplifying means comprises;

sense amplifying means for amplifying the output signal of the column address selecting means by using a first stand-by signal and an equalizing signal as control signals; and

precharging means for precharging the sense amplifying means by using the first stand-by signal as a control signal;

second data signal amplifying means for amplifying an output signal from the first data signal amplifying means; and

data signal transferring means for transferring an output signal of the second data signal amplifying means to output to buffering means.

2. The high sensitive data signal amplifying circuit according to claim 1, wherein the bit line amplifying means comprises a latch type sense amplifier comprising cross-coupled CMOS transistors, each said CMOS transistor comprising a PMOS transistor and an NMOS transistor.

3. The high sensitive data signal amplifying circuit according to claim 1, wherein the sense amplifying means comprises:

a first current mirror type sense amplifier for amplifying differential voltage of a first output signal relative to a second output signal of the column address selecting means;

a second current mirror type sense amplifier for amplifying differential voltage of the second output signal relative to the first output signal of the column address selecting means; and

first equalizing means for controlling output signals of the first and the second current mirror type sense amplifiers.

4. The high sensitive data signal amplifying circuit according to claim 3, wherein the first current mirror sense amplifier comprises:

first and second PMOS transistors comprising sources coupled to a power voltage and aligned in current mirror type;

a first NMOS transistor comprising a gate connected to the second output signal of the column address selecting means and a drain coupled to a drain of the first PMOS transistor;

a second NMOS transistor comprising a gate connected to the first output signal of the column address selecting means and a drain coupled to a drain of the second PMOS transistor; and

a third NMOS transistor comprising a drain coupled to the sources of the first and the second NMOS transistors and a gate connected to the first stand-by signal,

wherein the output signal is outputted from the drain of first PMOS transistor.

5. The high sensitive data signal amplifying circuit according to claim 3, wherein the second current mirror sense amplifier comprises:

first and second PMOS transistors comprising sources coupled to a power voltage and having a mirror type alignment;

a first NMOS transistor comprising a gate connected to the first output signal of the column address selecting means and a drain coupled to a drain of the first PMOS transistor;

a second NMOS transistor comprising a gate connected to the second output signal of the column address selecting means and a drain coupled to a drain of the second PMOS transistor; and

a third NMOS transistor comprising a drain coupled to the sources of the first and the second NMOS transistors and a gate connected to the first stand-by signal,

wherein the output signal is outputted from the drain of first PMOS transistor.

6. The high sensitive data signal amplifying circuit according to claim 3, wherein the first equalizing means comprises:

a third PMOS transistor, comprising a gate connected to the equalizing signal, for coupling the drains of the first and the second PMOS transistors of the first current mirror type sense amplifier;

a fourth PMOS transistor, comprising a gate connected to the equalizing signal, for coupling the drains of the first and the second PMOS transistors of the second current mirror type sense amplifier; and

a fifth PMOS transistor, comprising a gate connected to the equalizing signal, for coupling the output signals of the first and the second current mirror type sense amplifiers.

7. The high sensitive data signal amplifying circuit according to claim 1, wherein the precharging means comprises:

a first precharging means for precharging the first current mirror type sense amplifier; and

a second precharging means for precharging the second current mirror type sense amplifier.

8. The high sensitive data signal amplifying circuit according to claim 7, wherein the first precharging means comprises:

third and fourth PMOS transistors, each said third and fourth PMOS transistors comprising a source coupled to the power voltage, wherein respective gates and drains of the third and the fourth transistors are coupled to each other;

a fifth PMOS transistor for coupling the drains of the third PMOS transistor and the first PMOS transistor of the first current mirror type sense amplifier, comprising a gate connected to the first stand-by signal; and

a sixth PMOS transistor for coupling the drains of the fourth PMOS transistor and the second PMOS transistor of the first current mirror type sense amplifier, comprising a gate connected to the first stand-by signal.

9. The high sensitive data signal amplifying circuit according to claim 7, wherein the second precharging means comprises:

third and fourth PMOS transistors, each said third and fourth PMOS transistors comprising a source coupled to the power voltage, wherein gates and sources of the third and the fourth transistors are coupled to each other;

a fifth EIMOS transistor, comprising a gate connected to the first stand-by signal, for coupling the drains of the third PMOS transistor and the first PMOS transistor of the second current mirror type sense amplifier; and

a sixth PMOS transistor, comprising a gate connected to the first stand-by signal, for coupling the drains of the fourth PMOS transistor and the second PMOS transistor of the second current mirror type sense amplifier.

10. The high sensitive data signal amplifying circuit according to claim 1, wherein the second data signal amplifying means comprises:

a latch type sense amplifier for amplifying an output signal of the first data signal amplifying means by using a second stand-by signal as a control signal; and

second equalizing means for controlling an output signal depending on the second stand-by signal.

11. The high sensitive data signal amplifying circuit according to claim 10, wherein the second equalizing means comprises:

first and second PMOS transistors, each said first and second PMOS transistors comprising a gate connected to the second stand-by signal, a source coupled to the power voltage and a drain coupled to the output of the latch type sense amplifier; and

a third PMOS transistor, comprising a gate connected to the second stand-by signal, for coupling the drains of the first and the second PMOS transistors.

12. The high sensitive data signal amplifying circuit according to claim 1, wherein the data signal transferring means comprises:

first and second inverters for inverting the first and second output signals of the second signal amplifying means;

a first NMOS transistor comprising a gate connected to an output signal of the first inverter, a source coupled to a ground voltage and a drain outputting an output signal to the buffering means; and

a second NMOS transistor comprising a gate connected to an output signal of the second inverter, a source coupled to a ground voltage and a drain outputting an output signal to the buffering means.