Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
First Claim
1. A multi-port register file memory, the memory comprising:
- at least one storage element;
at least one read port coupled to said storage element; and
a sensing device comprising input offset and gain stages coupled to said read port and adapted to sense a small voltage swing.
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Reexamination
Accused Products
Abstract
Devices and methods relating to a multi-port register file memory including a plurality of storage elements in columns are disclosed. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.
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Citations
40 Claims
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1. A multi-port register file memory, the memory comprising:
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at least one storage element;
at least one read port coupled to said storage element; and
a sensing device comprising input offset and gain stages coupled to said read port and adapted to sense a small voltage swing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A multi-port register file memory, the memory comprising:
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a plurality of storage elements arranged in a plurality of columns, each of said columns having at least one bitline;
at least one read port coupled to said storage element;
a sensing device having a predetermined trip point coupled to said read port and adapted to sense a small voltage swing; and
a biasing device adapted to bias at least one of said bitlines at a predetermined relationship to said trip point.
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22. A multi-port register file memory, the memory comprising:
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a plurality of storage elements arranged in columns;
means for selecting one of said storage elements; and
means for sensing a small bitline voltage swing, said sensing means comprising input offset and gain stages. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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30. A circuit for use with a memory having at least one storage element, the circuit comprising:
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a read port coupled to the storage element; and
a sensing amplifier comprising input offset and gain stages coupled to said read port and adapted to sense a small voltage swing. - View Dependent Claims (31, 32, 33, 34, 35)
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36. A method for improving speed and increasing performance in a multi-port register file memory having a plurality of storage elements, the method comprising:
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selecting at least one of said storage elements; and
sensing a small voltage swing using a sensing device comprising input offset and gain stages. - View Dependent Claims (37)
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38. A method for reading data stored in a multi-port register file memory having a plurality of memories arranged in columns, the method comprising:
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selecting one of the columns;
flowing a current through at least one transistor to one of the storage elements in said one column;
causing an output of a sense amplifier, comprising input offset and gain stages, connected to at least said column to switch to a high state. - View Dependent Claims (39, 40)
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Specification