Shared memory apparatus and method for multiprocessor systems

• US 6,519,672 B2
• Filed: 05/10/2001
• Issued: 02/11/2003
• Est. Priority Date: 03/19/1999
• Status: Expired due to Term

• Current Assignee: III Holdings 4, LLC
• Original Assignee: Times N Systems
• Inventors: West, Lynn Parker, Scardamalia, Theodore G.
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US09/854,351
• Publication Number:
  US 20020026493A1
• Time in Patent Office: 642 Days
• Field of Search: 710/316,317,305 711/100,147,148,149,150,154 709/213,214
• US Class Current: 710/317
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

A memory alias adapter, coupled to a processor'"'"'s memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor'"'"'s memory access on the memory bus. As a result, it is transparent to the processor whether its memory access is to the local memory or to the shared memory.

Claims

1. A shared memory unit for providing shared memory to a plurality of processor systems, the shared memory unit comprising:

a shared memory comprising a plurality of memory banks;

a plurality of input/output ports, each input/output port being connectable to a processor system by a dedicated data link;

means coupled to the input/output ports for receiving a shared memory access request from a requesting processor;

means coupled to the receiving means for determining the memory bank corresponding to the memory access request;

connecting means coupled to the receiving means, the determining means, and the memory banks, for providing a data path between the input/output port and the memory bank associated with the memory access request;

a memory controller coupled to the connecting paeans and the receiving means, the memory controller performing memory accesses to the shared memory bank through the connecting means in accordance with the memory access request; and

means coupled to the memory controller and the input/output ports for generating a shared memory access response for transmission back to the requesting processor system.

2. The shared memory unit according to claim 1, wherein the connecting means comprises a crossbar switch.

3. The shared memory unit according to claim 2, wherein the crossbar switch comprises a non-blocking crossbar switch.

4. The shared memory unit according to claim 1, wherein at least one of the input/output ports comprises a Scalable Coherent Interface.

5. The shared memory unit according to claim 1, wherein at least one of the input/output ports comprises an IEEE 1394 interface.

6. The shared memory unit according to claim 1, wherein at least one of the input/output ports comprises a SCSI bus interface.

7. The shared memory unit according to claim 1, wherein at least one of the input/output ports comprises an Ethernet network interface.

8. The shared memory unit according to claim 1, wherein the shared memory unit further includes means for providing atomic memory operations between at least one of the processor systems and the shared memory.

9. A memory bus transfer controller for controlling accesses to a local portion of distributed shared memory, the memory bus transfer controller comprising:

a local processor memory bus interface coupling the memory bus transfer controller to a local processor and to a memory private to the local processor;

a local shared memory bus interface coupling the memory bus transfer controller to the local portion of distributed shared memory;

a shared memory interconnect bus coupling the memory bus transfer controller to at least one remote memory bus transfer controller associated with at least one remote processor;

first monitoring means coupled to the local processor memory bus interface for monitoring local processor memory bus accesses;

first determining means coupled to the first monitoring means for determining whether a memory address associated with the processor memory bus access corresponds to one of the memory private to the local processor, the local portion of distributed shared memory, and a remote portion of distributed shared memory;

second monitoring means coupled to the shared memory interconnect bus for monitoring remote processor memory access requests;

second determining means coupled to the second monitoring means for determining when a remote processor memory access request corresponds to the local portion of distributed a shared memory; and

a memory controller coupled to the first determining means, the second determining means, the local processor memory bus, and the shared memory interconnect bus, the memory controller performing a local shared memory access when the first determining means indicates that a local processor memory bus access corresponds to the local portion of distributed shared memory, sending a shared memory access request to the shared memory interconnect bus when the first determining means indicates that a local processor memory bus access corresponds to a remote portion of distributed shared memory, and performing a local shared memory bus access when the second determining means indicates that a remote memory access request corresponds to the local portion of distributed shared memory;

whereby it is transparent to the local processor whether each of its memory access operations is addressed to the local memory, the local portion of distributed shared memory, or a remote portion of distributed shared memory.