Method and system for processing pipelined memory commands

• US 6,519,689 B2
• Filed: 01/16/2001
• Issued: 02/11/2003
• Est. Priority Date: 08/27/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/764,567
• Publication Number:
  US 20010027506A1
• Time in Patent Office: 756 Days
• Field of Search: 710/34, 710/36, 710/37, 711/167, 711/169
• US Class Current: 711/169
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal. Thus, the start command signal is generated after the flag signal by a delay that corresponds to the type of memory command and the clock speed. The latched command bits and the start command signal are applied to a command processor that executes the commands in a pipeline using a sequencer to generate a sequence of timing signals, and generates command signals from the latched command bits. The specific timing signal used is a function of the type of memory operation corresponding to the command bits and the clock speed. The command processor generates and applies an acknowledgment signal to the command unit upon receipt of the start command signal. The command unit is available to receive a new command upon receipt of the acknowledgment signal.

Claims

1. In a memory device receiving memory commands, a method for processing the memory commands, comprising:

requesting a memory command in response to receipt of an acknowledgment signal;

storing the memory command and asserting a busy signal in response thereto;

generating command signals by preprocessing the memory command;

providing the command signals for execution of a command; and

deasserting the busy signal responsive to receipt of the acknowledgment signal and requesting another memory command.

2. The method of claim 1 wherein providing the command signals for execution of a command comprises providing a start signal to initiate execution of the command.

3. The method of claim 1 wherein the timing of generating command signals and providing the command signals for execution of a command is dependent on the frequency of a system clock.

4. The method of claim 1, further comprising storing an initial value in a counter and decrementing the initial value, and generating the command signals is in response to initiating decrementing.

5. The method of claim 4 providing the command signals occurs when the initial value is decremented to a first value.

6. In a memory device receiving memory commands, a method for processing the memory commands, comprising:

distributing memory commands to one of a plurality of command units for processing in response to the command unit receiving an acknowledgment signal;

each command unit generating command signals in response to receiving a memory command; and

each command unit providing the command signals for execution of a command, and subsequently requesting receipt of another memory command in response to receiving the acknowledgement signal from a command processor to which the command signals were provided.

7. The method of claim 6 wherein distribution of the memory commands to the command units is performed in an hierarchical manner.

8. The method of claim 6 wherein the command signals generated by the command units include a start signal to initiate execution of the command.

9. The method of claim 6, further comprising deasserting a busy signal prior to requesting receipt of another memory command.

10. The method of claim 6 wherein the timing between generating the command signals and providing the same for execution is dependent on the frequency of a system clock.

11. A method of processing memory commands applied to a memory device, comprising:

storing a plurality of command bits of a memory command;

decrementing an initial value stored in a counter;

pre-processing the stored command bits to generate at least one command signal;

providing the at least one command signal and a start signal to initiate processing of the command signal in response to the initial value decrementing to a command count value;

generating an acknowledgment signal in response to receiving the at least one command signal and start signal; and

prior to decrementing the initial value to zero and in response to receiving the acknowledgment signal, requesting receipt of another memory command.

12. The method of claim 11, further comprising resetting the counter for storage of the initial value.

13. The method of claim 11 wherein the initial value stored in the counter is provided by the memory command.

14. The method of claim 11 wherein the initial value stored in the counter is dependent on the frequency of a system clock.

15. The method of claim 11, further comprising asserting a busy signal subsequent to storing the command bits.

16. The method of claim 15, further comprising deasserting the busy signal in response to receiving the acknowledgment signal.

17. A method for processing memory commands applied to a memory device, comprising:

receiving a memory command and storing an initial value in a counter;

decrementing the initial value;

pre-processing the memory command to generate command signals representing an internal command;

initiating execution of the internal command represented by the command signals in response to the initial value decrementing to a first value;

prior to initial value being decremented to a terminal value, requesting receipt of another memory command.

18. The method of claim 17 wherein the first value is determined by a system clock frequency.

19. The method of claim 17 wherein requesting receipt of another memory command is in response to receiving an acknowledgment signal from a processing unit to which the command signals were provided.

20. The method of claim 17 wherein initiating execution of the internal command comprises providing the command signals and a start signal to a processing unit.

21. The method of claim 17, further comprising generating an active busy signal in response to receiving the memory command, and requesting receipt of another memory command comprises deactivating the busy signal.

22. The method of claim 17 wherein the terminal value is zero.