Vacuum package fabrication of integrated circuit components

• US 6,521,477 B1
• Filed: 02/02/2000
• Issued: 02/18/2003
• Est. Priority Date: 02/02/2000
• Status: Expired due to Term

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Gooch, Roland W., Schimert, Thomas R.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Luu, Chuong A
• Application Number:
  US09/496,820
• Time in Patent Office: 1,112 Days
• Field of Search: 438/51, 438/401, 438/909, 438/113, 438/106, 438/50
• US Class Current: 438/106
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/909 Controlled atmosphere

Abstract

A method for vacuum packaging MEMS or similar devices during device fabrication comprises forming a plurality of MEMS devices (12), or similar devices, on a device wafer (10). A device sealing ring (16) is formed between the MEMS devices (12) and bonding pads (14) connected to a MEMS device. A solder adhesion layer (24) forms part of the device sealing ring (16) surrounding each MEMS or similar device (12). A lid wafer (30) is formed having a plurality of lid sealing rings (32) corresponding in number and location to the device sealing rings (16). Each lid sealing ring (32) surrounds a cavity (34). The device wafer (30) is aligned with the lid wafer (10) to align each device sealing ring (16) with the corresponding lid sealing ring (32), leaving a gap between the lid wafer (30) and the device wafer (10). The resulting assembly (50) is placed in a vacuum furnace. The vacuum furnace is evacuated and heated to a temperature sufficient to allow outgassing of all surface areas of the lid wafer (30) and the device (10). The device wafer (30) is brought into contact with the lid wafer (10) thereby creating a vacuum package over each MEMS device (12). The assembly (50) is cooled at a rate sufficient to minimize subsequent outgassing of the surfaces while minimizing thermal stresses upon the vacuum package. After the assembly (50) is cooled, each vacuum packaged MEMS device (12) is tested, and the assembly (50) is then diced into individual vacuum packaged MEMS devices (12).

Claims

1. A method for vacuum packaging integrated circuit devices, comprising:

forming on a device wafer a plurality of integrated circuit devices;

forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit devices and one or more bonding pads coupled to each of the one or more integrated circuit devices;

forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;

forming a sealing layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;

aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer; and

mating the device wafer with the lid wafer in a vacuum environment to form a vacuum package within each of the plurality of first sealing rings and second sealing rings, each vacuum package enclosing one or more of the plurality of integrated circuit devices.

2. The method of claim 1, further comprising:

forming a plurality of cavities on the lid wafer, each of the plurality of cavities formed within and surrounded by one of the plurality of second sealing rings.

3. The method of claim 2, wherein forming a plurality of cavities comprises etching a plurality of pits in the lid wafer, each pit surrounded by one of the plurality of second sealing rings thereby leaving a cavity surrounded by one of the plurality of second sealing rings.

4. The method of claim 2, wherein forming a plurality of cavities comprises:

etching a plurality of holes in a window wafer corresponding to the plurality of integrated circuit devices; and

bonding the window wafer to the lid wafer thereby creating a plurality of cavities corresponding to the plurality of integrated circuit devices.

5. The method of claim 1, wherein mating the device wafer with the lid wafer comprises:

placing the aligned device wafer and lid wafer in a vacuum chamber;

generating a vacuum within the vacuum chamber; and

closing the gap between the device wafer and lid wafer thereby contacting the plurality of first sealing rings with the plurality of second sealing rings creating a plurality of vacuum packages, each vacuum package enclosing one or more of the plurality of integrated circuit devices.

6. The method of claim 1, wherein mating the device wafer with lid wafer comprises:

placing the aligned device wafer and lid wafer in a vacuum furnace;

generating a vacuum within the vacuum furnace;

outgassing surface areas of the device wafer and the lid wafer by heating the vacuum furnace to a temperature sufficient to outgas the surface areas;

closing the gap between the device wafer and lid wafer thereby contacting the plurality of first sealing rings with the plurality of second sealing rings creating a plurality of vacuum packages, each vacuum package enclosing one or more of the plurality of integrated circuit devices; and

cooling the device wafer and lid wafer assembly after closing the gap at a rate determined to minimize subsequent outgassing of surfaces within the plurality of vacuum packages while minimizing thermal stresses on the plurality of vacuum packages.

7. The method of claim 1, wherein forming a sealing layer comprises forming an indium compression seal on each of the second sealing rings.

8. The method of claim 1, wherein forming a plurality of first sealing rings comprises first forming a plurality of dielectric layer rings, each of the plurality of dielectric layer rings surrounding one or more integrated circuit devices, each dielectric layer ring positioned between the perimeter of the one or more integrated circuit device and one or more bonding pads coupled to each of the one or more integrated circuit devices.

9. The method of claim 1, further comprising:

coating the inner surface of the lid wafer within each of the second sealing rings with an anti-reflective coating; and

coating the outer surface of the lid wafer with an anti-reflective coating.

10. The method of claim 1, further comprising:

forming one or more spacers on the plurality of second sealing rings.

11. The method of claim 1, further comprising:

forming one or more bonding pad channels in the lid wafer corresponding in location to the bonding pads on the device wafer.

12. The method of claim 1, further comprising:

opening a plurality of probe access channels in the lid wafer following the formation of a plurality of vacuum packages, the plurality of probe access channels

providing access to the bonding pads for testing of a plurality of vacuum packaged integrated circuit devices;

testing each of the plurality of vacuum packaged integrated circuit devices by probing the bonding pads coupled to each integrated circuit device; and

dicing the plurality of vacuum packaged integrated circuit devices following testing thereof.

13. A method for vacuum packaging integrated circuit devices, comprising:

forming on a device wafer a plurality of integrated circuit devices;

forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit device and one or more bonding pads coupled to each of the one or more integrated circuit devices;

forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;

depositing a solder layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;

aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer; and

mating the device wafer with the lid wafer in a vacuum environment to form a plurality of vacuum packages, each vacuum package enclosing one or more of the plurality of integrated circuit devices.

14. The method of claim 13, further comprising:

heating the solder layer prior to mating the device wafer with the lid wafer.

15. The method of claim 13, wherein depositing a solder layer comprises positioning a preform solder pattern on the lid wafer in alignment with either the plurality of first sealing rings or the plurality of second sealing rings.

16. The method of claim 13, wherein depositing a solder layer comprises electroplating the lid wafer to deposit the solder layer.

17. The method of claim 13, wherein depositing a solder layer comprises vacuum deposition of the solder layer.

18. The method of claim 13, wherein depositing a solder layer comprises electroless plating.

19. A method for vacuum packaging integrated circuit devices, comprising:

forming on a device wafer a plurality of integrated circuit devices;

forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit device and one or more bonding pads coupled to each of the one or more integrated circuit devices;

forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;

forming a solder layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;

aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer; and

mating the device wafer with the lid wafer in a vacuum environment to form a plurality of vacuum packages, each vacuum package enclosing one or more of the plurality of integrated circuit devices.

20. The method of claim 19, wherein forming a plurality of first sealing rings comprises forming a solder adhesion surface on each of the plurality of first sealing rings.

21. The method of claim 20, wherein forming a solder adhesion surface comprises:

depositing a layer of titanium;

depositing a layer of palladium on the layer of titanium; and

depositing a layer of gold on the layer of palladium.

22. The method of claim 19, wherein forming a plurality of second sealing rings comprises forming on a lid wafer a plurality of solder adhesion surfaces corresponding in number and location to the plurality of first sealing rings.

23. The method of claim 22, wherein forming a plurality of solder adhesion surfaces comprises:

depositing a layer of titanium;

depositing a layer of palladium on the layer of titanium; and

depositing a layer of gold on from the layer of palladium.

24. A method for vacuum packaging integrated circuit devices, comprising:

forming on a device wafer a plurality of integrated circuit devices;

forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit devices and one or more bonding pads coupled to each of the one or more integrated circuit devices;

forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;

forming a sealing layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;

aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer;

placing the aligned device wafer and lid wafer in a vacuum furnace leaving a gap between the device wafer and the lid wafer;

generating a vacuum within the vacuum furnace;

outgassing surface areas of the device wafer and the lid wafer by heating the vacuum furnace to a temperature sufficient to outgas the surface areas;

closing the gap between the device wafer and lid wafer thereby contacting the plurality of first sealing rings with the plurality of second sealing rings creating a plurality of vacuum packages, each vacuum package enclosing one or more of the plurality of integrated circuit devices; and

cooling the device wafer and lid wafer assembly after closing the gap at a rate determined to minimize subsequent outgassing of surfaces within the plurality of vacuum packages while minimizing thermal stresses on the plurality of vacuum packages.

25. The method of claim 24 wherein forming a sealing layer comprises forming a compression seal on each of the second sealing rings.

26. The method of claim 24 further comprising:

forming one or more spacers on the plurality of second sealing rings.

27. The method of claim 24 further comprising:

forming one or more bonding pad channels in the lid wafer corresponding in location to the bonding pads on the device wafer.

28. A method for vacuum packaging integrated circuit devices, comprising:

forming on a device wafer a plurality of integrated circuit devices;

forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit devices and one or more bonding pads coupled to each of the one or more integrated circuit devices;

forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;

forming a sealing layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;

aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer;

placing the aligned device wafer and lid wafer in a vacuum chamber leaving the gap between the device wafer and the lid wafer;

generating a vacuum within the vacuum chamber; and

closing the gap between the device wafer and lid wafer thereby contacting a plurality of first sealing rings with the plurality of second sealing rings creating a plurality of vacuum packages, each vacuum package enclosing one or more of the plurality of integrated circuit devices.

29. The method of claim 28 wherein forming a sealing layer comprises forming a compression seal on each of the second sealing rings.

30. The method of claim 28 further comprising:

forming one or more spacers on the plurality of second sealing rings.

31. The method of claim 28 further comprising:

forming one or more bonding pad channels in the lid wafer corresponding in location to the bonding pads on the device wafer.