Manufacturing method for a semiconductor device

• US 6,521,482 B1
• Filed: 08/03/2000
• Issued: 02/18/2003
• Est. Priority Date: 08/06/1999
• Status: Expired due to Term

• Current Assignee: Ebara Corporation, Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Shibasaki, Takanori, Hyoudo, Haruo, Kimura, Shigeo
• Primary Examiner(s): Smith, Matthew S.
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US09/632,170
• Time in Patent Office: 929 Days
• Field of Search: 438/110, 438/108, 438/127, 438/613, 438/113, 438/616, 438/618, 438/612, 438/615, 438/114, 438/458, 438/464, 438/465, 438/106, 438/125, 438/112, 438/121, 438/122
• US Class Current: 438/110
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

A method of manufacturing individual semiconductor devices by forming island sections 26 on the surface of a common substrate 21, forming electrodes 27 and 28 one on either side of each island section 26, die bonding a semiconductor chip 29 to each island section 26, and wire bonding the electrodes 27 and 28 to the semiconductor chip 29. A single common cover 36 is fixed over the entire surface of the common substrate 21 to form a hermetically sealed hollow space over each chip mounting section 41. The cover 36 and substrate 21 are separated at each mounting section 41 to form individual semiconductor devices.

Claims

1. A method of manufacturing semiconductor devices, comprising:

preparing a common substrate plate having opposing first and second main surfaces and being formed of an insulating material, a plurality of mounting areas being provided at said first main surface, each of said mounting areas being provided with an island section for mounting a semiconductor chip and electrode sections for connecting electrodes of the semiconductor chip, said second main surface being provided with a plurality of external connecting electrodes connected to said island sections and said electrode sections, respectively;

fixing a semiconductor chip on each of said island sections;

fixing a common cover member over said mounting areas so that said semiconductor chips are respectively disposed in hermetically sealed hollow spaces defined between said cover member and said common substrate plate; and

cutting through said common substrate plate and said common cover member to separate said common substrate plate and said common cover member into plural semiconductor devices having said semiconductor chips disposed in said hermetically sealed hollow spaces, respectively, between individual substrate plates and individual cover members, respectively.

2. A method as claimed in claim 1, wherein, in said preparing of said common substrate plate, said common substrate plate is provided with a plurality of depressions at said first main surface, each of said depressions containing one of said mounting areas and defining one of said hollow spaces.

3. A method as claimed in claim 2, wherein said common cover member comprises a common cover member plate.

4. A method as claimed in claim 1, wherein said common cover member is provided with a plurality of depressions arranged such that, after said cover member is fixed to said common substrate plate, each of said depressions contains one of said mounting areas and defines one of said hollow spaces.

5. A method as claimed in claim 4, wherein said common cover member comprises a common cover member plate.

6. A method as claimed in claim 1, wherein said common cover member comprises a common cover member plate.

7. A method as claimed in claim 1, wherein, in said preparing of said common substrate plate, said common substrate plate is prepared such that, for each of said mounting areas, said electrode sections are disposed on opposing sides of said island section.

8. A method as claimed in claim 1, wherein, in said preparing of said common substrate plate, said common substrate plate is prepared such that, for each of said mounting areas, said island section extends across an approximate center of said mounting area and is disposed between said electrode sections.

9. A method as claimed in claim 1, wherein, in said preparing of said common substrate plate, said external connecting electrodes are respectively connected to said island sections and said electrode sections through via holes formed in said common substrate plate.

10. A method as claimed in claim 1, wherein said cutting of said common substrate plate and said common cover member comprises a dicing process.

11. A method as claimed in claim 1, wherein said preparing of said common substrate plate and said cutting of said common substrate plate and said common cover member are carried out such that, for each of said semiconductor devices, each of said external connecting electrodes is set back from an edge of said semiconductor device.

12. A method as claimed in claim 1, wherein said preparing of said common substrate plate and said cutting of said common substrate plate and said common cover member are carried out such that, for each of said semiconductor devices, each of said external connecting electrodes is set back 0.1-0.2 mm from an edge of said semiconductor device.

13. A method as claimed in claim 1, wherein said preparing of said common substrate plate and said cutting of said common substrate plate and said common cover member are carried out such that, for each of said semiconductor devices, each of said external connecting electrodes does not extend sideways outwardly from said semiconductor device.

14. A method as claimed in claim 1, further comprising providing a common side portion frame that forms sidewalls of said hollow spaces.

15. A method as claimed in claim 14, wherein said providing of said common side portion frame comprises providing a second substrate having a lattice structure to be disposed between said common cover member and said first main surface of said common substrate plate.

16. A method as claimed in claim 14, wherein said common side portion frame is formed as an integral part of said common cover member.