Method of manufacturing a field effect transistor

• US 6,521,497 B2
• Filed: 05/09/2001
• Issued: 02/18/2003
• Est. Priority Date: 11/14/1997
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Mo, Brian Sze-Ki
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Roman, Angel
• Application Number:
  US09/854,102
• Publication Number:
  US 20010023104A1
• Time in Patent Office: 650 Days
• Field of Search: 438/270, 438/272, 438/589, 438/268, 438/269
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of manufacturing a trenched field effect transistor that includes a heavy body structure. The method includes forming a plurality of trenches into a semiconductor substrate having dopants of a first conductivity type, wherein the gate electrode of the transistor is formed. A doped well having dopants of a second conductivity type is formed into the substrate and between the trenches. Source regions having dopants of the first conductivity type are formed inside the doped well adjacent to and on opposite sides of the trenches. A heavy body region having dopants of the second conductivity type is formed inside each doped well and at a depth that is shallower than the doped well. The heavy body is formed in a manner that makes an abrupt junction between the heavy body and the well. In one embodiment, the abrupt junction is formed by a dobule implant process.

Claims

1. A method of making a heavy body structure for a trenched DMOS transistor comprising:

providing a semiconductor substrate;

forming a plurality of trenches into the substrate;

implanting a first dopant at a first energy and dosage into the substrate, to form a doped well;

implanting, into said well and between adjacent trenches, a second dopant at a second energy and dosage to form a first doped portion of a heavy body; and

implanting, into said well and between adjacent trenches, a third dopant at a third energy and dosage to form a second doped portion of said heavy body,

wherein the first portion of the heavy body is deeper than the second portion of the heavy body, and wherein said dosage of said second dopant has a doping concentration that is greater than said dosage of said third dopant.

2. The method of claim 1 wherein said first and second dopants both comprise boron.

3. The method of claim 1 wherein said first energy is from about 30 to 100 keV.

4. The method of claim 3 wherein said first dosage is from about 1E13 to 1E15 cm⁻

2.

5. The method of claim 1 wherein said second energy is from about 150 to 200 keV.

6. The method of claim 5 wherein said second dosage is from about 1E15 to 5E15 cm⁻

2.

16. The method of claim 1 wherein said third dopant comprises boron and said third dosage is from about 1E14 to 1E15cm⁻

2.

17. The method of claim 16 wherein said third energy is from about 20 to 40 keV.

7. A method of manufacturing a trenched field effect transistor comprising:

forming an epitaxial layer on a semiconductor substrate;

patterning and etching a plurality of trenches into the epitaxial layer;

lining each trench with a gate dielectric layer;

depositing polysilicon to fill the dielectric-lined trenches;

doping the polysilicon with a dopant of a first type;

patterning the epitaxial layer and implanting a dopant of a second, opposite type, in regions between adjacent trenches, to form a plurality of wells interposed between said adjacent trenches;

patterning the epitaxial layer and implanting a dopant of the second type, in regions between adjacent trenches, to form a plurality of second dopant type contact areas and a plurality of heavy bodies positioned within the wells;

patterning the epitaxial layer and implanting a dopant of the first type to provide source regions and first dopant type contact areas; and

applying a dielectric to the surface of the semiconductor substrate and patterning the dielectric to expose electrical contact areas,

wherein the implanting step for forming the heavy bodies comprises implanting a first dopant at a first energy and dosage and a second dopant at a second energy and dosage, said second energy and dosage being less than said first energy and dosage, respectively.

8. The method of manufacturing a trenched field effect transistor of claim 7 wherein the trenches are patterned to extend in one direction and be substantially parallel to each other.

9. The method of manufacturing a trenched field effect transistor of claim 7 wherein the patterning and implanting steps further comprise arranging the first dopant type contact areas and second dopant type contact areas in alternation and extend linearly between adjacent trenches.

10. The method of manufacturing a tenched field effect transistor of claim 7 wherein the implanting step for forming the source regions comprises implanting a first dopant at a first energy and dosage and a second dopant at a second energy and dosage, the second energy and dosage being less than the first energy and dosage, respectively.

11. The method of manufacturing a trenched field effect transistor of claim 7 wherein the heavy bodies are formed prior to forming the source regions.

12. The method of manufacturing a trenched field effect transistor of claim 7 wherein the source regions are formed prior to the heavy bodies.

13. The method of manufacturing a trenched field effect transistor of claim 7 further comprising a step of forming a field termination structure around a periphery of the field effect transistor.

14. The method of manufacturing a trenched field effect transistor of claim 13 wherein said field termination structure is formed by forming a deep well doped with a dopant of the second dopant type.

15. The method of manufacturing a trenched field effect transistor of claim 7 wherein said dielectric is applied before the steps of forming the heavy bodies and second dopant type contact areas, and the dielectric provides a mask for the patterning of the heavy bodies and second dopant type contacts.

18. The method of manufacturing a trenched field effect transistor of claim 13 wherein said field terminations structure is formed by forming a trench ring.