Solid phase epitaxy activation process for source/drain junction extensions and halo regions

• US 6,521,502 B1
• Filed: 08/07/2000
• Issued: 02/18/2003
• Est. Priority Date: 08/07/2000
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/633,207
• Time in Patent Office: 925 Days
• Field of Search: 438/302, 438/303, 438/305, 438/528
• US Class Current: 438/305
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method of manufacturing an integrated circuit may include the steps of forming a deep amorphous region and doping the deep amorphous region. The doping of the deep amorphous region can form source and drain regions with extensions. After doping, the substrate is annealed. The annealing can occur at a low temperature.

Claims

1. A method of manufacturing a transistor, the method comprising in the following order:

providing a gate structure;

providing a deep amorphous implant;

providing a shallow extension dopant implant;

providing a tilted angle halo dopant implant, the tilted angle halo implant being the only halo implant step;

forming a pair of spacers abutting the gate structure;

providing a deep source/drain dopant implant; and

annealing at a very low temperature, the annealing recrystallizing an amorphous region formed by the deep amorphous implant and activating dopants from the shallow extension dopant implant, the halo dopant implant, and the deep source/drain dopant implant via solid phase epitaxy wherein the deep amorphous implant is performed before the deep source/drain dopant implant and the deep source/drain dopant implant is performed after the tilted halo dopant implant.

2. The method of claim 1, wherein the deep amorphous implant creates an amorphous region at least 100 nm deep.

3. The method of claim 1, wherein the step of annealing comprises providing a furnace anneal to recrystallize an amorphous region formed by the deep amorphous implant.

4. The method of claim 1, wherein the gate structure comprises a gate insulator of a high-k material.

5. The method of claim 1, wherein the shallow extension dopant implant has a center projected to a depth of 10-15 Å

deep.

6. The method of claim 5, wherein the step of annealing is at a temperature below 600°

C.

7. The method of claim 6, wherein the temperature is at least between approximately 500°

C. and 600°

C.

8. The method of claim 1, wherein the tilted angle halo dopant implant is performed at an angle of 10-30 degrees.

9. A process of forming a transistor on a substrate, the substrate including a gate conductor, the process comprising in the following order:

forming a deep amorphous region;

doping a shallow portion of the deep amorphous region for shallow source and drain extensions;

doping a halo region at least partially in the deep amorphous region with a tilted implant, the halo region sharing a top border with a bottom border of the source extension;

doping a deep portion of the deep amorphous region for deep source and drain regions; and

recrystallizing the deep amorphous region, wherein the deep amorphous region is formed before the deep source and drain regions and the deep source and drain regions are formed after the halo region.

10. The process of claim 9, wherein the step of recrystallizing comprises a rapid thermal anneal (RTA).

11. The process of claim 10, wherein the RTA uses a temperature substantially between 500°

and 600°

C.

12. The process of claim 9, wherein the doping the halo region utilizes a tilted angle implant.

13. The process of claim 9, wherein the doping the shallow region is an implant projected to a depth of less than 16 Å

.

14. A method of manufacturing a transistor on an ultra-large scale integrated circuit, the method comprising the steps of:

amorphizing a deep region in a substrate, the deep region having a depth of between 100 and 200 nm;

implanting a dopant into a shallow portion of the deep region of the substrate to form source and drain extensions;

implanting a single halo region in a single step in the substrate before the first implanting step, the halo region being implanted at a dose between 1×

10¹³-1×

10¹⁴ dopants per square centimeter at an energy level of 5-50 KeV;

implanting a dopant into a deep portion of the deep region to form deep source and drain regions; and

recrystallizing the deep region, and activating the deep source and drain regions in a very low temperature process, wherein the deep region is formed before the deep source and drain regions and the deep source and drain regions are formed after the halo region is formed.

15. The method of claim 14, wherein the halo region is formed by a tilted implant after the source and drain extensions.

16. The method of claim 14, wherein the halo region is shallower than the deep source and drain regions.

17. The method of claim 14, wherein recrystallizing comprises applying a rapid thermal anneal between approximately 500°

and 600°

C.

18. The method of claim 14, further comprising doping the substrate with a tilt angle implant to form a halo region.

19. The method of claim 18, wherein the first implanting has a projection depth with a center between 10-15 Å

.

20. The method of claim 14, wherein the gate insulator is any one of Ai₂O₃, TiO₂, and ZrO₂.