Method for shallow trench isolation with removal of strained island edges

• US 6,521,510 B1
• Filed: 03/25/2002
• Issued: 02/18/2003
• Est. Priority Date: 03/23/2001
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Fisher, Philip, Chan, Darin A.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Mai, Anh Duy
• Application Number:
  US10/105,998
• Time in Patent Office: 330 Days
• Field of Search: 438/424, 438/426, 438/435
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material

Abstract

A method of isolation of active islands on a silicon-on-insulator semiconductor device, including steps of (1) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate; (2) etching through the silicon active layer to form an isolation trench, the isolation trench defining an active island in the silicon active layer, the active island having at least one upper sharp corner; (3) rounding the at least one upper sharp corner of the active island, whereby at least one strained edge portion of the active island is formed; (4) removing at least a part of the at least one strained edge portion; and (5) at least partially filling the isolation trench with a dielectric trench isolation material to form a shallow trench isolation structure. An SOI wafer semiconductor device having a STI isolation structure free from a strained edge portion and a bird'"'"'s beak.

Claims

1. A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of:

providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate;

etching through the silicon active layer to form an isolation trench, the isolation trench defining an active island in the silicon active layer, the active island having at least one upper sharp corner;

rounding the at least one upper sharp corner of the active island, whereby at least one strained edge portion of the active island is formed;

removing at least a part of the at least one strained edge portion; and

at least partially filling the isolation trench with a dielectric trench isolation material to form a shallow trench isolation structure.

2. The method of claim 1, wherein the step of removing includes using a hard mask layer as an etch mask, leaving at least a part of the strained edge portion unmasked.

3. The method of claim 2, wherein the step of removing includes trimming the hard mask layer.

4. The method of claim 2, wherein the step of etching the unmasked part of the strained edge portion etches through a portion of the active island to the dielectric insulation layer.

5. The method of claim 1, further comprising steps of forming a pad oxide, a hard mask and a photoresist prior to the step of etching through the silicon active island.

6. The method of claim 3, further comprising a further step of corner rounding following the trimming.

7. The method of claim 1, wherein at least a partially rounded corner remains on the active island following the step of removing the strained edge portion.

8. The method of claim 1, wherein after the isolation trench is partially filled, a further step of corner rounding is carried out.

9. The method of claim 8, wherein following the further step of corner rounding, the isolation trench is filled.

10. The method of claim 1, further comprising a step of oxidizing silicon on sidewalls of the isolation trench.

11. The method of claim 10, where in the step of oxidizing silicon on sidewalls occurs substantially simultaneously with the step of rounding the at least one upper sharp corner.

12. The method of claim 10, wherein the step of the step of oxidizing silicon on sidewalls takes place after the step of removing the strained edge portion.

13. The method of claim 10, wherein the step of oxidizing silicon on sidewalls forms a trench oxide liner in the isolation trench.

14. The method of claim 10, wherein the trench oxide liner and the dielectric insulation layer form an integral isolation structure for and define the active island.

15. A method of shallow trench isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of:

providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate;

forming a hard mask layer over the silicon active layer;

etching through the hard mask layer and the silicon active layer to form an isolation trench, the isolation trench defining an active island in the silicon active layer, the active island having at least one upper sharp corner;

rounding the at least one upper sharp corner of the active island to form at least one upper rounded corner, whereby at least one strained edge portion of the active island is formed;

trimming the hard mask layer;

removing at least a part of the at least one strained edge portion by etching the at least one strained edge portion using the trimmed hard mask layer as an etch mask; and

filling the isolation trench with a dielectric trench isolation material to form a shallow trench isolation structure.

16. The method of claim 15, wherein each of the dielectric insulation layer and the dielectric trench isolation material is silicon dioxide.