MIS transistor and manufacturing method thereof

• US 6,521,519 B2
• Filed: 01/26/2001
• Issued: 02/18/2003
• Est. Priority Date: 12/10/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shimizu, Satoshi, Oda, Hidekazu
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex H.
• Application Number:
  US09/769,400
• Publication Number:
  US 20010008293A1
• Time in Patent Office: 753 Days
• Field of Search: 438/184, 438/303, 438/366, 438/581, 438/595, 438/664, 438/682
• US Class Current: 438/595
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

This invention provides a MIS transistor with less electrical short between a gate and source/drain electrodes. A sidewall spacer 15 has a two-layer structure including a buffer layer 13 which consists of nitrided oxide silicon and a silicon nitrided layer 14 formed on the buffer layer 13. The sidewall spacer 15 serves as a mask to form a silicide film 10.

Claims

1. A manufacturing method of a MIS transistor comprises:

forming a gate insulation film and a gate electrode, both of a MIS transistor, on a silicon substrate;

forming a sidewall spacer including a silicon nitride layer, on both sides of said gate electrode on said silicon substrate in contact with said silicon substrate, and including a buffer nitrided oxide silicon layer on both sides of said gate electrode on said silicon substrate and in contact with said silicon substrate, wherein said buffer nitrided oxide silicon layer has a peak of nitrogen concentration on an interface with said silicon substrate, and the nitrogen concentration in said buffer nitrided oxide silicon layer declines with distance from said silicon substrate; and

forming a silicide film outside of said sidewall spacer in said silicon substrate by using a metal to be diffusion species for silicon in silicide reaction.

2. The manufacturing method of a MIS transistor of claim 1, said step of forming a silicide film including a step of:

making cobalt silicide of cobalt and silicon with a single rapid thermal annealing.

3. The manufacturing method of a MIS transistor of claim 1, wherein said metal to be diffusion species for silicon consists of cobalt.

4. The manufacturing method of a MIS transistor of claim 1, wherein said metal to be diffusion species for silicon consists of nickel.

5. The manufacturing method of a MIS transistor of claim 1, wherein said metal to be diffusion species for silicon consists of alloy including cobalt.

6. The manufacturing method of a MIS transistor of claim 1, wherein said metal to be diffusion species for silicon consists of alloy including nickel.