High performance integrated varactor on silicon

• US 6,521,939 B1
• Filed: 09/29/2000
• Issued: 02/18/2003
• Est. Priority Date: 09/29/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Yeo, Kiat-Seng, Do, Manh-Anh, Geng, Chun Qi, Chew, Kok-Wai, Ma, Jian Guo
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/672,764
• Time in Patent Office: 872 Days
• Field of Search: 438/197, 438/203, 438/211, 438/379, 257/312, 257/595, 257/598, 257/29.345, 257/296
• US Class Current: 257/312
• CPC Class Codes: H01L 27/0808 Varactor diodes
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.

Claims

1. A varactor device comprising:

a bottom electrode comprising a plurality of diffusion junctions in a semiconductor substrate wherein said diffusion junctions are arranged in a two-dimensional array;

a dielectric layer overlying said semiconductor substrate;

a top electrode overlying said dielectric layer wherein said top electrode comprises a single polygon containing a two-dimensional array of openings therein that expose said diffusion junctions and a two-dimensional array of top electrode locations wherein said too electrode locations are surrounded by four said diffusion junctions;

an interlevel dielectric layer overlying said top electrode and said diffusion junctions wherein said interlevel dielectric layer has a two-dimensional array of contact openings that expose underlying said diffusion junctions; and

a patterned metal layer overlying said interlevel dielectric layer and contacting said diffusion junctions through said contact openings.

2. The device according to claim 1 wherein said semiconductor substrate comprises a doping type of the group of:

n-type and p-type.

3. The device according to claim 1 wherein said diffusion junctions comprise one of the group of:

n-type doping and p-type doping.

4. The device according to claim 1 further comprising a well junction in said semiconductor substrate wherein said diffusion junctions are contained in said well junctions.

5. The device according to claim 4 wherein said well junction comprises one of the group of:

n-well and p-well.

6. The device according to claim 1 wherein said dielectric layer comprises silicon dioxide.

7. The device according to claim 1 wherein said top electrode comprises polysilicon.

8. The device according to claim 1 wherein said interlevel dielectric layer comprises silicon dioxide.

9. The device according to claim 1 wherein said metal layer comprises one of the group of:

aluminum and aluminum alloys.

11. The device according to claim 9 wherein said dielectric layer comprises silicon dioxide.

12. The device according to claim 9 wherein said top electrode comprises a polysilicon layer.

13. The device according to claim 9 wherein said interlevel dielectric layer comprises silicon dioxide.

14. The device according to claim 9 wherein said metal layer comprises one of the group of:

aluminum and aluminum alloys.

10. A varactor device comprising:

a bottom electrode comprising a plurality of diffusion junctions in a semiconductor substrate wherein said diffusion junctions are arranged in a two-dimensional array, wherein said diffusion junctions are n-type, and wherein said diffusion junctions are contained in an n-well junction;

a dielectric layer overlying said diffusion junctions;

a top electrode overlying said dielectric layer wherein said top electrode comprises a single polygon containing a two-dimensional array of openings therein that expose said diffusion junctions and a two-dimensional array of top electrode locations wherein said top electrode locations are surrounded by four said diffusion junctions;

an interlevel dielectric layer overlying said top electrode and said diffusion junction wherein said interlevel dielectric layer has a two-dimensional array of contact openings that expose underlying said diffusion junction; and

a patterned metal layer overlying said interlevel dielectric layer and contacting said diffusion junction through said contact openings.

15. A method to form a varactor device in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;

forming a dielectric layer overlying said semiconductor substrate;

depositing a top electrode layer overlying said dielectric layer;

patterning said top electrode layer to form a top electrode wherein a single polygon containing a two dimensional array of openings and a two-dimensional array of top electrode locations is formed therein;

thereafter implanting ions into said semiconductor substrate through said two-dimensional array of openings to thereby form a two-dimensional array of diffusion junctions wherein said top electrode locations are surrounded by four said diffusion junctions;

thereafter depositing an interlevel dielectric layer overlying said top electrode and said diffusion junctions;

patterning said interlevel dielectric layer to form a two-dimensional array of contact openings to underlying said diffusion junctions;

depositing a metal layer overlying said interlevel dielectric layer and filling said contact openings; and

patterning said metal layer to complete the manufacture of said integrated circuit device.

16. The method according to claim 15 wherein said diffusion junctions comprises one of the group of:

n-type doped junction and p-type doped junction.

17. The method according to claim 15 further comprising forming a well junction in said semiconductor substrate before said step of forming a dielectric layer wherein said well junction comprises one of the group of:

n-well and p-well and wherein said diffusion junctions are contained in said well junction.

18. The method according to claim 15 wherein said dielectric layer comprises silicon dioxide.

19. The method according to claim 15 wherein said top electrode layer comprises polysilicon.

20. The method according to claim 15 wherein said interlevel dielectric layer comprises silicon dioxide.