MOSFET technology for programmable address decode and correction
First Claim
1. A circuit switch, comprising:
- a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide;
a wordline coupled to the gate;
a first transmission line coupled to the source region;
a second transmission line coupled to the drain region; and
wherein the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).
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Abstract
Structures and methods for PLA capability on a DRAM chip according to a DRAM optimized process flow are provided by the present invention. These structures and methods include using MOSFET devices as re-programmable elements in memory address decode circuits in a DRAM integrated circuit. The structures and methods use the existing process sequence for MOSFET'"'"'s in DRAM technology. An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. The MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2), such that the programmed MOSFET operates at reduced drain source current.
108 Citations
33 Claims
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1. A circuit switch, comprising:
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a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide;
a wordline coupled to the gate;
a first transmission line coupled to the source region;
a second transmission line coupled to the drain region; and
wherein the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2). - View Dependent Claims (2, 3, 4, 6, 7)
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5. A circuit switch, comprising:
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a n-channel metal oxide semiconductor field effect transistor (NMOS) in a substrate, the NMOS having a source region, a drain region, a channel region between the source and region regions, and a gate separated from the channel region by a gate oxide;
a wordline coupled to the gate;
a source line operatively coupled to source region;
a bitline operatively coupled to the drain region; and
wherein the NMOS is a programmed NMOS having an electron charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2), Vt2 having a higher voltage threshold than Vt1.
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8. A non-volatile, reprogrammable switch, comprising:
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a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate oxide;
a wordline coupled to the gate;
a first transmission line coupled to the source region;
a second transmission line coupled to the drain region; and
wherein the MOSFET is a programmed MOSFET having an electron charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt1) adjacent to the drain region and a second voltage threshold region (Vt2) adjacent to the source region, the Vt2 having a greater voltage threshold than Vt1.
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9. A latch on a substrate, comprising:
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a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate oxide;
a first transmission line coupled to the gates of a first inverter in the cross coupled pair and to the drain regions of a second inverter in the cross coupled pair;
a second transmission line coupled to the gates of a second inverter in the cross coupled pair and to the drain regions of a first inverter in the cross coupled pair; and
wherein at least one of the MOSFETs is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2). - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A programmable decoder, comprising:
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an array of latches on a substrate, wherein each latch comprises;
a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide;
a number of first transmission lines coupled to the gates of the a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a second inverter in the cross coupled pair of inverters in the array of latches;
a number of second transmission lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a first inverter in the cross coupled pair of inverters in the array of latches; and
wherein at least one latch includes a MOSFET which is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2). - View Dependent Claims (17, 18, 19, 20)
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21. An integrated circuit, comprising:
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an array of latches on a substrate, wherein each latch comprises;
a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a source region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate oxide;
a number of first transmission lines coupled to the gates of the a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a second inverter in the cross coupled pair of inverters in the array of latches;
a number of second transmission lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a first inverter in the cross coupled pair of inverters in the array of latches;
an address driver coupled to the number of first transmission lines;
a number of row drivers and at least one redundant row driver coupled to the number of second transmission lines; and
wherein at least one latch includes a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2). - View Dependent Claims (22, 23, 24, 25, 26, 27)
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28. An electronic system, comprising:
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a memory; and
a processor coupled to the memory, wherein the memory includes a programmable decoder, the programmable decoder comprising;
an array of latches on a substrate, wherein each latch includes a pair of cross coupled inverters, wherein each inverter includes an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS), each MOSFET has a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate oxide, and wherein the NMOS and PMOS of each inverter are coupled at the drain region;
a number of address input lines coupled to the gates of a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain region of a second inverter in the cross coupled pair of inverters in the array of latches;
a number of output lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain region of a first inverter in the cross coupled pair of inverters in the array of latches; and
wherein at least one of the MOSFETs in the array of latches is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region of the programmed MOSFET has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2). - View Dependent Claims (29, 30, 31, 32, 33)
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Specification