SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same

• US 6,521,959 B2
• Filed: 02/13/2001
• Issued: 02/18/2003
• Est. Priority Date: 10/25/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sung-Dae, Kim, Min-Su, Kang, Hee-Sung, Kim, Byung-Sun, Kim, Kwang-Il, Kim, Young-Wug, Ko, Young-Gun
• Primary Examiner(s): Nguyen, Tuan H.
• Assistant Examiner(s): Schillinger, Laura M
• Application Number:
  US09/782,116
• Publication Number:
  US 20010031518A1
• Time in Patent Office: 735 Days
• Field of Search: 257/397, 257/347, 257/510, 257/515, 257/514, 257/513, 257/52, 257/408, 257/288, 257/236, 257/396, 257/398, 257/400, 257/344, 438/221, 438/300, 438/296, 438/297
• US Class Current: 257/397
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Claims

1. A silicon-on-insulator (SOI) semiconductor integrated circuit formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer, the integrated circuit comprising:

a transistor active region comprising a predetermined region of the semiconductor layer;

at least one body contact active region spaced apart from the transistor active region, the body contact active region including a portion of the semiconductor layer;

a semiconductor residue layer disposed over the entire surface of the buried insulating layer between the transistor active region and the body contact active region, the semiconductor residue layer being thinner than the semiconductor layer;

a partial trench isolation layer surrounding upper sidewalls of the transistor active region and the body contact active region, the partial trench isolation layer being disposed on the semiconductor residue layer;

a full trench isolation layer interposed between the partial trench isolation layer and the transistor active region, the full trench isolation layer being in contact with the buried insulating layer;

a body extension of the first conductivity type extended from a predetermined sidewall of the semiconductor residue layer toward the transistor active region, the body extension electrically connecting the transistor active region to the semiconductor residue layer and being covered with the partial trench isolation layer; and

an insulated gate pattern crossing over the transistor active region, the insulated gate pattern being overlapped with the body extension.

2. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the first conductivity type is one of P-type and N-type.

3. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the semiconductor layer is a silicon layer.

4. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the full trench isolation layer comprises a first full trench isolation layer and a second full trench isolation layer, which are separated each other.

5. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 4, wherein the first and second full trench isolation layers are symmetrical to the insulated gate pattern each other.

6. The silicon-on-insulator (SOT) semiconductor integrated circuit of claim 1, further comprises source/drain regions formed at the transistor active regions, which are located at both sides of the insulated gate pattern, the source/drain regions having a second conductivity type opposite to the first conductivity type and being in contact with the buried insulating layer.

7. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 6, wherein the full trench isolation layer surrounds the source/drain regions.

8. The silicon-on-insulator (SOT) semiconductor integrated circuit of claim 1, further comprises a well contact region formed at the body contact active region, the well contact region having the first conductivity type.