High voltage MOS devices

• US 6,521,962 B2
• Filed: 02/05/2001
• Issued: 02/18/2003
• Est. Priority Date: 12/09/2000
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Evans, Ivor Robert
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US09/775,943
• Publication Number:
  US 20020072186A1
• Time in Patent Office: 743 Days
• Field of Search: 257/341, 257/361, 257/213, 257/409, 257/410, 257/408, 257/491, 257/492, 257/493, 438/306, 438/286
• US Class Current: 257/409
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A P channel high voltage metal oxide semiconductor device is described which is integrated in the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices. The high voltage device has a lightly doped p⁻ drift region adjacent to the heavily doped p⁺ drain region. A high voltage support region is formed directly below the drift region using high energy ion implantation with an implantation energy of between about 2 and 3 Mev. This high energy ion implantation is used to precisely locate the high voltage support region directly below the drift region. This high voltage support region avoids punch-through from the P channel drain through the drift region into the substrate while using a standard depth for the n type well. This allows the high voltage device to be integrated into the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices.

Claims

1. A high voltage metal oxide semiconductor device, comprising:

a substrate of p type silicon having between about 5×

10¹⁹ and 1.3×

10²⁰ impurity atoms/cm³;

an epitaxial layer of p type silicon having between about 1×

10³⁵ and 3×

10¹⁵ impurity atoms/cm³ formed on said substrate;

a first well, having a first channel region, formed within said epitaxial layer wherein said first well is n type silicon having between about 1×

10¹⁶ and 4×

10¹⁶ impurity atoms/cm³ and said first channel region has a first edge and a second edge;

a drift region formed in said first well adjacent to said second edge of said first channel region wherein said drift region is p type silicon having between about 3×

10¹⁶ and 7×

10¹⁶ impurity atoms/cm³;

a high voltage support region formed in said first well directly below said drift region wherein said high voltage support region is n type silicon having between about 5×

10¹⁵ and 2×

10¹⁶ impurity atoms/cm³;

a thick oxide formed directly above said drift region;

a first gate formed on a first gate oxide above said first well and directly above said first channel region;

a first source formed in said first well adjacent to said first edge of said first channel region wherein said first source is p type silicon having between about 5×

10¹⁵ and 2×

10¹⁶ impurity atoms/cm³; and

a first drain formed in said first well adjacent to said drift region so that said drift region is between said first channel region and said first drain wherein said first drain is p type silicon having between about 5×

10¹⁹ and 2×

10²⁰ impurity atoms/cm³.

2. The high voltage metal oxide semiconductor device of claim 1 wherein said high voltage support region is formed using ion implantation of phosphorous ions using an ion implantation energy of between about 2 and 3 Mev, thereby enabling said high voltage support region to be located directly below said drift region.

3. The high voltage metal oxide semiconductor device of claim 1 wherein said thick oxide is a silicon oxide.

4. The high voltage metal oxide semiconductor device of claim 1 wherein said first gate oxide is a silicon oxide.

5. The high voltage metal oxide semiconductor device of claim 1 wherein said first gate extends from said first edge of said first channel region to said second edge of said second channel region.

6. The high voltage metal oxide semiconductor device of claim 1 wherein the operating voltage between said first source and said first drain is 35 volts or less.

7. The high voltage metal oxide semiconductor device of claim 1, further comprising:

a second well of n type silicon having between about 1×

10¹⁶ and 4×

10¹⁶ impurity atoms/cm³ formed in said epitaxial layer outside of said first well;

a second source of p type silicon formed in said second well;

a second drain of p type silicon formed in said second well, thereby defining a second channel region in said second well between said second source and said second drain; and

a second gate electrode and a second gate oxide formed over said second channel region.

8. The high voltage metal oxide semiconductor device of claim 1, further comprising:

a third source of n type silicon formed in said epitaxial layer outside of said first well;

a third drain of n type silicon formed in said epitaxial layer outside of said first well, thereby defining a third channel region in said epitaxial layer outside of said first well and between said third source and said third drain; and

a third gate electrode and a third gate oxide formed over said third channel region.