Wafer-level package

• US 6,521,995 B1
• Filed: 09/30/1999
• Issued: 02/18/2003
• Est. Priority Date: 06/28/1999
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Wood, Alan G., Akram, Salman
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/409,536
• Time in Patent Office: 1,237 Days
• Field of Search: 757/737, 757/738, 757/774, 757/778, 757/668
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention. Such a chip-scale package includes a semiconductor device invertedly disposed over the carrier such that bond pads of the semiconductor device substantially align with apertures formed through the carrier. Thus, the bond pads of the semiconductor device may communicate with the conductive bumps by means of the conductive material disposed in the apertures of the carrier. Methods of fabricating the carrier of the present invention and methods of fabricating chip-scale packages including the carrier are also within the scope of the present invention.

Claims

1. A carrier for use in a chip-scale package, comprising:

a preformed polymeric film, said preformed polymeric film having a first surface configured to be disposed in substantial contact with an active surface of a semiconductor device;

at least one conductive via extending substantially longitudinally through said preformed polymeric film prior to placement thereof upon said active surface of said semiconductor device, electrically exposed at said first surface of said preformed polymeric film, and positioned to directly contact at least one bond pad of said semiconductor device; and

at least one contact pad positionable directly over said at least one bond pad, in contact with said at least one conductive via, and substantially electrically exposed at a second surface of said preformed polymeric film.

2. The carrier of claim 1, wherein said at least one conductive via comprises a conductive bump.

3. The carrier of claim 2, wherein said at least one conductive bump comprises solder.

4. A chip-scale package, comprising:

a polymeric carrier including at least one aperture extending substantially longitudinally therethrough between an active surface-abutting surface of said polymeric cartier and a contact beating surface of said polymeric carrier;

a contact pad disposed over said at least one aperture;

a semiconductor device including an active surface having at least one bond pad thereon and exposed to said at least one aperture, said active surface-abutting surface of said polymeric carrier in substantial contact with said active surface and secured thereto with adhesive material disposed between said polymeric carrier and said active surface.

5. The chip-scale package of claim 4, wherein said at least one aperture includes conductive material therein.

6. The chip-scale package of claim 5, wherein said conductive material communicates with said at least one bond pad.

7. The chip-scale package of claim 6, wherein said conductive in aerial is disposed directly adjacent said at least one bond pad.

8. The chip-scale package of claim 6, further comprising a contact in communication with said conductive material.

9. The chip-scale package of claim 8, further comprising a conductive bump adjacent said contact.

10. The chip-scale package of claim 7, wherein said conductive bump comprises solder.

11. The chip-scale package of claim 5, wherein said conductive material comprises a conductive bump.

12. The chip-scale package of claim 5, further comprising a conductive elastomer disposed over said conductive material.

13. The chip-scale package of claim 12, further comprising at least one conductive bump disposed on said conductive elastomer, opposite said conductive material, and in communication therewith.

14. The chip-scale package of claim 4, wherein said at least one aperture and said at least one bond pad are substantially aligned.

15. The chip-scale package of claim 4, wherein said preformed polymeric carrier at least partially contacts a peripheral edge of said semiconductor device.