Self-timed CMOS static logic circuit

• US 6,522,170 B1
• Filed: 04/27/1998
• Issued: 02/18/2003
• Est. Priority Date: 04/27/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Klim, Peter Juergen, Durham, Christopher McCall
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/067,153
• Time in Patent Office: 1,758 Days
• Field of Search: 326/93-98, 326/21
• US Class Current: 326/93
• CPC Class Codes: H03K 19/0966 Self-timed logic

Abstract

A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.

Claims

1. A self-timed logic circuit comprising:

a first transparent latch register operable for receiving one or more input data signals from one or more sources;

a control circuit operable for receiving one or more valid signals, wherein each one of the one or more valid signals is associated with a particular input data signal;

a combinatorial static logic block comprising one or more static logic circuits, wherein the control circuit;

clocks the one or more input data signals from the first transparent latch register to the combinatorial static logic block when all of the one or more valid signals are received by the control circuit, wherein the combinatorial static logic block produces one or more output data signals; and

a second transparent latch register operable for receiving the one or more output data signals.

2. The circuit as recited in claim 1, wherein the control circuit clocks the one or more output data signals through the second transparent latch register after the combinatorial static logic block has produced the one or more output data signals.

3. The circuit as recited in claim 2, wherein the control circuit sends one or more output valid signals in association with the one or more output data signals, wherein the one or more output data signals and the one or more output valid signals are sent to one or more sink circuits.

4. The circuit as recited in claim 2, wherein the combinatorial static logic block produces the one or more output data signals after a designated period of time.

5. The circuit as recited in claim 1, wherein the control circuit is operable for sending one or more complete signals to the one or more source circuits in response to receipt of all of the one or more valid signals.

6. A self-timed logic circuit comprising:

a first transparent latch register operable for receiving one or more input data signals from one or more sources;

a control circuit operable for receiving one or more valid signals wherein each one of the one or more valid signals is associated with a particular input data signal;

a combinatorial static logic block comprising one or more static logic circuits, wherein the control circuit clocks the one or more input data signals from the first transparent latch register to the combinatorial static logic block when all of the one or more valid signals are received by the control circuit, wherein the combinatorial static logic block produces one or more output data signalsl;

a second transparent latch register operable for receiving the one or more output data signals,

wherein the control circuit clocks the one or more output data signals through the second transparent latch register after the combinatorial static logic block has produced the one or more output data signals,

wherein the control circuit sends one or more output valid signals in association with the one or more output data signals, wherein the one or more output data signals and the one or more output valid signals are sent to one or more sink circuits; and

circuitry in the control circuit for maintaining the one or more output data signals until all of one or more complete signals, associated with the one or more output data signals, are received from the one or more sink circuits.

11. The circuit as recited in claim 6, wherein the delay circuit propagates a rising edge of its input signal at a slower rate than a falling edge to its output.

7. A self-timed logic circuit comprising:

a first transparent latch register operable for receiving one or more input data signals, from one or more sources;

a control circuit operable for receiving one or more valid signals, wherein each one of the one or more valid signals is associated with a particular input data signal;

a combinatorial static logic block comprising one or more static logic circuits, wherein the control circuit clocks the one or more input data signals from the first transparent latch register to the combinatorial static logic block when all of the one or more valid signals are received by the control circuit, wherein the combinatorial static logic block produces one or more output data signals;

a second transparent latch register operable for receiving the one or more output data signals,

wherein the control circuit clocks the one or more output data signals through the second transparent latch register after the combinatorial static logic block has produced the one or more output data signals,

wherein the combinatorial static logic block produces the one or more output data signals after a designated period of time; and

a delay circuit operable for producing a delayed signal in response to the one or more valid signals, wherein the clocking of the one or more output data signals through the second transparent latch register is performed in response to the delayed signal.

8. The circuit as recited in claim 7, wherein timing of the delay circuit roughly corresponds to an amount of time it takes for the combinatorial static logic block to produce the one or more output data signals from the one or more input data signals.

9. The circuit as recited in claim 8, wherein the delay circuit produces the delayed signal after the one or more output data signals are outputted to the second transparent latch register.

10. The circuit as recited in claim 7, wherein the control circuit further comprises:

a Mueller C-Element operable for receiving the one or more valid signals;

a first AND gate having an input coupled to an output of the Mueller C-Element;

a first rising edge one-shot having an input coupled to an output of the first AND gate, wherein an output of the first rising edge one-shot is coupled to a clock input of the first transparent latch register;

a set/reset latch having a set input coupled to the output of the first rising edge one-shot, wherein an output of the set/reset latch is coupled to an input of the delay circuit;

a second AND gate having an input coupled to an output of the delay circuit; and

a second rising edge one-shot having an input coupled to an output of the second AND gate, wherein an output of the second rising edge one-shot is coupled to a clock input of the second transparent latch register.