CMOS switch with linearized gate capacitance
First Claim
Patent Images
1. A compensation circuit for a CMOS switch, the compensation circuit comprising:
- a nonlinear gate capacitance compensation circuit coupled to the CMOS switch; and
biasing circuitry for providing a substantially fixed bias voltage that is coupled to the nonlinear gate capacitance compensation circuit, the biasing circuitry that provides the substantially fixed bias voltage to the nonlinear gate capacitance compensation circuit when the CMOS switch is in an ON state.
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Abstract
A CMOS switch with compensation circuitry that maintains linearized gate capacitance, said switch capable of selectively processing a signal independent of changes to gate capacitance current. The switch passes signals which are substantially insensitive to changes in source impedance. Thus, the switch processes an analog signal with a minimum of distortion as a result of gate capacitance currents.
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Citations
21 Claims
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1. A compensation circuit for a CMOS switch, the compensation circuit comprising:
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a nonlinear gate capacitance compensation circuit coupled to the CMOS switch; and
biasing circuitry for providing a substantially fixed bias voltage that is coupled to the nonlinear gate capacitance compensation circuit, the biasing circuitry that provides the substantially fixed bias voltage to the nonlinear gate capacitance compensation circuit when the CMOS switch is in an ON state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of using a gate capacitance compensation circuit for maintaining a substantially constant gate capacitance of a CMOS switch, the gate capacitance compensation circuit being biased with a fixed bias voltage, the CMOS switch having an N-channel device and a P-channel device, and the CMOS switch receiving an input voltage, the method comprising:
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compensating a non-linear gate capacitance current in the N-channel device at a first threshold level of the input voltage; and
compensating a non-linear gate capacitance current in the P-channel device at a second threshold level of the input voltage. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method of using a gate capacitance compensation circuit for maintaining a gate capacitance of a CMOS switch substantially constant, the gate capacitance compensation circuit being biased with a fixed bias voltage, a first drain-source connected switch being coupled between an input voltage and the CMOS switch and a second drain-source connected switch being coupled between the CMOS switch and a voltage output, the method comprising:
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turning on an N-channel portion of the first drain-source connected switch and an N-channel portion of the second drain-source connected switch substantially simultaneously to turning OFF a P-channel portion of the CMOS switch; and
turning on a P-channel portion of the first drain-source connected switch and a P-channel portion of the second drain-source connected switch substantially simultaneously to turning OFF an N-channel portion of the CMOS switch.
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20. A method of using a gate capacitance compensation circuit for maintaining a gate capacitance of a CMOS switch substantially constant, the gate capacitance compensation circuit being biased with a fixed bias voltage, a first drain-source connected switch being coupled between an input voltage and the CMOS switch and a second drain-source connected switch being coupled between the CMOS switch and a voltage output, the method comprising:
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turning ON an N-channel portion of the first drain-source connected switch and an N-channel portion of the second drain-source connected switch, and turning OFF a P-channel portion of the CMOS switch at a first level of the input voltage to the CMOS switch; and
turning ON a P-channel portion of the first drain-source connected switch and a P-channel portion of the second drain-source connected switch, and turning OFF an N-channel portion of the CMOS switch at a second level of the input voltage.
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21. A multiplexer circuit comprising:
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a plurality of CMOS switches;
a nonlinear gate capacitance compensation circuit for compensating non-linear gate capacitance current in at least one of the plurality of CMOS switches; and
wherein the gate capacitance compensation circuit is biased with a fixed bias voltage.
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Specification