Method and apparatus for optimum biasing of cascaded MOSFET radio-frequency devices

• US 6,522,197 B2
• Filed: 12/21/2000
• Issued: 02/18/2003
• Est. Priority Date: 04/21/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Paradigm Wireless Systems, Inc. (REMEC, Inc.)
• Inventors: Nam, Ki Y., Do, Thinh Dat
• Primary Examiner(s): Nguyen, Patricia T.
• Application Number:
  US09/746,440
• Publication Number:
  US 20020005755A1
• Time in Patent Office: 789 Days
• Field of Search: 330/133, 330/149, 330/278
• US Class Current: 330/133
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers

Abstract

Generally, the invention relates to a method and apparatus to improve the performance of multi-stage radio frequency linear power amplifiers. More particularly, the present invention discloses a cascaded gain expansion stage and gain compression stage at differing bias levels to produce an amplifier with superior linearity and lower intermodulation distortion and adjacent channel power than any single stage by alone.

Claims

1. A cascaded multi-stage power amplifier, comprising:

a first stage amplifier biased to operate in a region of gain expansion; and

a second stage amplifier coupled to the first stage amplifier and biased to operate in a region of gain compression, the second stage including a plurality of amplifiers in a parallel configuration, the plurality of amplifiers being biased at different operating points selected to reduce adjacent band power.

2. The power amplifier of claim 1, wherein the power amplifier is a radio frequency amplifier.

3. The power amplifier of claim 1, wherein the power amplifier includes at least one lateral diffusion metal oxide semiconductor power transistor.

4. The power amplifier of claim 1, wherein the cascaded first and second stage amplifiers exhibit a more linear gain than either stage alone.

5. The power amplifier of claim 1, wherein the intermodulation distortion of the cascaded first and second stage amplifiers is less than the intermodulation distortion of either stage alone.

6. The power amplifier of claim 1, further comprising at least one controller circuit to bias the first stage and second stage amplifiers.

7. The power amplifier of claim 6, further comprising a memory store, wherein the at least one controller sets the bias to the first stage according to values found in the memory store.

8. The power amplifier of claim 1, wherein the first stage amplifier is adaptively biased as the output of the power amplifier is varied.

9. The power amplifier of claim 1, wherein the first stage amplifier is adaptively biased to compensate for temperature variations of the power amplifier.

10. A method to minimize intermodulation distortion and reduce adjacent band power of a multi-stage power amplifier, comprising:

biasing a first stage amplifier to operate in a region of gain expansion; and

biasing a second stage amplifier, which is coupled to the first stage amplifier, to operate in a region of gain compression, the second stage amplifier having a plurality of amplifiers in a parallel configuration, the biasing including biasing the plurality of amplifiers of the second stage at different operating points selected to reduce adjacent band power.

11. The method of claim 10 wherein biasing the first and second stage amplifiers results in a more linear gain than either stage alone.

12. The method of claim 10, wherein the intermodulation distortion of the cascaded first and second stage amplifiers is less than the intermodulation distortion of either stage alone.

13. The method of claim 10, wherein the amplifier is a radio frequency amplifier.

14. The method of claim 10, wherein the power amplifier includes at least one lateral diffusion metal oxide semiconductor power transistor.

15. The method of claim 10, wherein the first and second stage amplifiers exhibit a more linear gain than either stage alone.

16. The method of claim 10, wherein biasing the first amplifier is accomplished according to values found in a memory store.

17. The method of claim 10, further comprising:

adaptively biasing the first stage amplifier as the output of the power amplifier is varied.

18. A cascaded multi-stage power amplifier, comprising:

a first stage amplifier; and

a second stage amplifier coupled to an output of the first stage amplifier, the second stage including a plurality of amplifiers in a parallel configuration, the plurality of amplifiers being biased at different operating points selected to reduce adjacent band power.

19. A cascaded multi-stage power amplifier, comprising:

an RF base station amplifier having;

a first stage amplifier; and

a second stage amplifier coupled to an output of the first stage amplifier, the second stage including a plurality of amplifiers in a parallel configuration, the plurality of amplifiers being biased at different operating points selected to reduce adjacent band power.

20. A method of reducing adjacent band power output of a cascaded multi-stage power amplifier comprising:

providing an output stage for the power amplifier having a plurality of amplifiers coupled in parallel; and

,

biasing the plurality of amplifiers at different operating points selected to reduce adjacent band power.

21. A method of reducing adjacent band power output of a cascaded multi-stage RF base station power amplifier comprising:

providing an output stage for the RF base station power amplifier having a plurality of amplifiers coupled in parallel; and

,

biasing the plurality of amplifiers at different operating points selected to reduce adjacent band power.