Semiconductor memory and method for accessing semiconductor memory
First Claim
1. A method of writing data to a semiconductor memory including a memory cell which comprises ferroelectric memory FETs each having a ferroelectric layer disposed between a gate electrode and a semiconductor layer, characterized in that a writing voltage is applied after applying a voltage that is opposite in direction to the writing voltage.
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Abstract
A method of accessing a semiconductor memory comprising ferroelectric memory FETs arranged as a matrix to allow write and/or read data to and from only an intended memory cell without the data in not-intended cells being destroyed by the application of a disturbing voltage to not-intended cells, even without providing each cell with a selection element. The method is characterized in that, when data are written to or read from memory cells Q1 through Q4 arranged as a matrix comprising ferroelectric memory FETs each having a ferroelectric layer on the gate side to constitute a semiconductor memory, a voltage of a direction opposite that of the voltage for writing or reading the data is applied, followed by the application of a voltage for writing or reading.
19 Citations
8 Claims
- 1. A method of writing data to a semiconductor memory including a memory cell which comprises ferroelectric memory FETs each having a ferroelectric layer disposed between a gate electrode and a semiconductor layer, characterized in that a writing voltage is applied after applying a voltage that is opposite in direction to the writing voltage.
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4. A method of reading data from a semiconductor memory including a memory cell which comprises ferroelectric memory FETs each having a ferroelectric layer disposed between a gate electrode and a semiconductor layer, characterized in that a reading voltage is applied after applying a voltage that is opposite in direction to the reading voltage.
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5. A method of accessing a semiconductor memory, the memory comprising memory cells comprising ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer, and buffer cells capable of transferring data from the memory cells, the method comprising the steps of;
- once transferring the data from the memory cell to the buffer cell, and writing again the transferred data to the memory cell so as to refresh the data in the memory cell.
- View Dependent Claims (6, 7, 8)
Specification