×

Memory array incorporating noise detection line

  • US 6,522,594 B1
  • Filed: 06/29/2001
  • Issued: 02/18/2003
  • Est. Priority Date: 03/21/2001
  • Status: Expired due to Term
First Claim
Patent Images

1. An integrated circuit comprising:

  • a memory array of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, the array having at least one layer of word lines and at least one layer of bit lines, the bit lines on each bit line layer organized in at least one group;

    at least one noise detection line associated with each layer of bit lines;

    a selection circuit for selecting one of a group of bit lines, and for selecting a noise detection line associated with the group of bit lines; and

    a bit line sensing circuit responsive to a signal on the selected bit line and a signal on the selected noise detection line.

View all claims
  • 10 Assignments
Timeline View
Assignment View
    ×
    ×