Memory array incorporating noise detection line

• US 6,522,594 B1
• Filed: 06/29/2001
• Issued: 02/18/2003
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/897,704
• Time in Patent Office: 599 Days
• Field of Search: 365/206, 365/94, 365/103, 365/104, 365/105, 365/175, 365/173, 365/171, 365/63, 365/51, 365/207, 365/225.7, 365/203
• US Class Current: 365/206
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Claims

1. An integrated circuit comprising:

a memory array of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, the array having at least one layer of word lines and at least one layer of bit lines, the bit lines on each bit line layer organized in at least one group;

at least one noise detection line associated with each layer of bit lines;

a selection circuit for selecting one of a group of bit lines, and for selecting a noise detection line associated with the group of bit lines; and

a bit line sensing circuit responsive to a signal on the selected bit line and a signal on the selected noise detection line.

2. The invention defined in claim 1 wherein:

each noise detection line is arranged so that memory cells coupled respectively thereto are substantially non-conductive.

3. The invention defined in claim 1 wherein:

memory cells forming each noise detection line are substantially non-conductive.

4. The invention defined in claim 1 wherein:

the bit line sensing circuit comprises a voltage sensing circuit.

5. The invention defined in claim 4 wherein the voltage sensing circuit comprises:

a first precharge circuit for precharging the selected noise detection line to an unselected word line bias voltage; and

a second precharge circuit for precharging the selected bit line to a voltage other than the unselected word line bias voltage.

6. The invention defined in claim 5 wherein:

the second precharge circuit is configured to precharge the selected bit line to ground.

7. The invention defined in claim 1 wherein:

the bit line sensing circuit comprises a current sensing circuit.

8. The invention defined in claim 1 wherein:

the selection circuit is arranged so that a selected bit line is never adjacent to a selected noise detection line.

9. The invention defined in claim 1 wherein:

the selection circuit is arranged so that a selected bit line is never adjacent to another selected bit line.

10. The invention defined in claim 1 wherein:

the selection circuit is arranged so that a selected bit line within a first group of bit lines is never adjacent to a selected bit line within a second group of bit lines.

11. The invention defined in claim 1 wherein the memory cells comprise a semiconductor material.

12. The invention defined in claim 1 wherein the memory cells comprise an organic polymer.

13. The invention defined in claim 1 wherein the memory cells comprise a phase change material.

14. The invention defined in claim 1 wherein the memory cells comprise an amorphous solid.

15. The invention defined in claim 1 wherein the memory cells comprise an anti-fuse layer.

16. The invention defined in claim 1 wherein the memory cells comprise a fuse layer.

17. The invention defined in claim 1 wherein:

the bit lines on each bit line layer are arranged in at least two groups, each group associated with a respective selection circuit and sensing circuit on a respective side of the array.

18. The invention defined in claim 17 wherein:

a single noise detection line is associated with more than one group of bit lines on a bit line layer and is selectable by the respective selection circuit for more than one group.

19. The invention defined in claim 17 wherein:

each respective group of bit lines on a bit line layer is associated with at least one respective noise detection line which is not also associated with at least one other group.

20. The invention defined in claim 17 wherein:

each noise detection line is arranged so that each memory cell coupled respectively thereto is arranged to conduct negligible current when an associated word line is selected.

21. The invention defined in claim 1 wherein:

each group of bit lines on a bit line layer includes a pair of associated noise detection lines.

22. The invention defined in claim 21 wherein:

half the respective memory cells on each noise detection line are arranged to conduct current when a respectively associated word line is selected, and the remaining half of the respective memory cells on each noise detection line are arranged to not conduct significant current when a respectively associated word line is selected.

23. The invention defined in claim 22 wherein:

the memory cells on each noise detection line are programmed during manufacture to provide testing of memory cell programmability.

24. The invention defined in claim 23 wherein:

the memory cells on each noise detection line are write-once programmable memory cells.

25. The invention defined in claim 21 wherein:

for a given word line, the associated memory cell on one but not the other of the pair of noise detection lines associated with a group of bit lines is conductive.

26. The invention defined in claim 25 wherein:

the selection circuit is arranged to select the noise detection line whose memory cell associated with the selected word line is not conductive.

27. The invention defined in claim 17 wherein:

the selection circuit is arranged so that a noise detection line adjacent to a selected bit line is never selected, irrespective of which group of bit lines each is associated with.

28. The invention defined in claim 17 wherein:

the selection circuit is arranged so that a selected bit line is never adjacent to another selected bit line, irrespective of which group of bit lines each is associated with.

29. The invention defined in claim 1 wherein:

the bit lines on each bit line layer are arranged in at least two groups, each group associated with a respective selection circuit and sensing circuit on a respective side of the array; and

each respective group of bit lines on a bit line layer includes a respective pair of noise detection lines exclusively associated with the respective group.

30. The invention defined in claim 29 wherein:

half the respective memory cells on each noise detection line are arranged to conduct current when a respectively associated word line is selected, and the remaining half of the respective memory cells on each noise detection line are arranged to not conduct significant current when a respectively associated word line is selected.

31. An integrated circuit comprising:

a multi-level memory array of programmable anti-fuse memory cells, having at least one layer of word lines and more than one layer of bit lines, the bit lines on each bit line layer organized in at least one group;

at least one noise detection line associated with each layer of bit lines;

a selection circuit for selecting, on a selected layer, one bit line of a group of bit lines, and a noise detection line associated with the group of bit lines; and

a bit line sensing circuit responsive to a signal on the selected noise detection line and a signal on the selected bit line.

32. The invention defined in claim 31 wherein:

memory cells on each noise detection line remain unprogrammed.

33. The invention defined in claim 31 wherein:

the bit line sensing circuit comprises a voltage sensing circuit.

34. The invention defined in claim 31 wherein:

the bit line sensing circuit comprises a current sensing circuit.

35. The invention defined in claim 31 wherein:

the selection circuit is arranged so that a selected bit line on a bit line layer is never adjacent to a selected noise detection line on the same bit line layer.

36. The invention defined in claim 31 wherein:

the selection circuit is arranged so that a selected bit line on a bit line layer is never adjacent to another selected bit line on the same bit line layer.

37. The invention defined in claim 31 wherein:

alternating bit lines on a bit line layer form a first group and are associated with a selection circuit and sensing circuit disposed to one side of the array, and remaining bit lines on the layer form a second group and are associated with a selection circuit and sensing circuit disposed to a side of the array opposite the one side.

38. The invention defined in claim 37 wherein:

each respective group of bit lines on a bit line layer is associated with a respective noise detection line.

39. The invention defined in claim 37 wherein:

memory cells on each noise detection line remain unprogrammed.

40. The invention defined in claim 37 wherein:

the selection circuit is arranged so that a selected bit line is never adjacent to a selected noise detection line, irrespective of which group of bit lines each is associated with.

41. The invention defined in claim 37 wherein:

the selection circuit is arranged so that a selected bit line is never adjacent to another selected bit line, irrespective of which group of bit lines each is associated with.

42. The invention defined in claim 37 further comprising:

more than one selection circuit associated with each group of bit lines.

43. The invention defined in claim 37 wherein:

the memory array is arranged with a word-line layer as the bottom-most layer of the memory array.

44. The invention defined in claim 37 wherein:

more than one noise detection line is associated with each selection circuit and sensing circuit; and

a noise detection line nearest to a selected bit line is selected.

45. The invention defined in claim 31 wherein:

each respective group of bit lines on a bit line layer is associated with a respective pair of noise detection lines.

46. The invention defined in claim 45 wherein:

half the memory cells on each noise detection line are programmed, and the remaining half of the memory cells on each noise detection line are unprogrammed.

47. The invention defined in claim 46 wherein:

the programmed memory cells on each noise detection line are programmed during manufacture to test programmability of write-once memory cells.

48. The invention defined in claim 46 wherein:

for a given word line, the associated memory cell on one but not the other of the pair of noise detection lines associated with a group of bit lines is programmed.

49. The invention defined in claim 48 wherein:

the selection circuit is arranged to select the noise detection line whose memory cell associated with the selected word line is unprogrammed.

50. An integrated circuit comprising:

a multi-level memory array of programmable anti-fuse memory cells, having at least one layer of word lines and more than one layer of bit lines;

at least one noise detection line associated with each layer of bit lines;

means for selecting a bit line on a layer and for selecting a noise detection line associated with the selected bit line;

means for comparing a noise current on the selected noise detection line plus a reference current, to a current on the selected bit line comprising a selected memory cell current and a noise current on the selected bit line.

51. The invention defined in claim 50 wherein:

the reference current has a magnitude between a current level corresponding to a programmed memory cell and a current level corresponding to an unprogrammed memory cell.