Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode

• US 6,522,599 B2
• Filed: 12/26/2001
• Issued: 02/18/2003
• Est. Priority Date: 06/10/1998
• Status: Expired due to Fees

• Current Assignee: DRAM Memory Technologies LLC (Acacia Research Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ishikawa, Masatoshi, Ooishi, Tsukasa
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US10/025,857
• Publication Number:
  US 20020064072A1
• Time in Patent Office: 419 Days
• Field of Search: 365/233, 365/230.01, 365/230.03, 365/230.06
• US Class Current: 365/189.15
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external clock signal is generated. The input/output buffer circuit is operated in synchronization with the internal clock signal.

Claims

1. A semiconductor memory device comprising:

a first interface circuit receiving a first external clock signal and a second external clock signal complementary to said first external clock signal from the outside of said semiconductor memory device, and generating a basal clock signal by comparing said first external clock signal with said second external clock signal;

a first internal clock generation circuit, based on said basal clock signal, generating a first internal clock signal for data output operation;

a second interface circuit operating based on said basal clock signal and receiving a command signal and an address signal;

a second internal clock generation circuit receiving a third external clock signal from the outside of said semiconductor memory device and generating a second internal clock signal; and

a third interface circuit including a data input circuit receiving input data in synchronization of said second internal clock signal.

2. The semiconductor memory device according to claim 1, wherein

said basal clock signal includes a first source clock signal and a second source clock signal complementary to said first source clock signal and

said first interface circuit includes a plurality of comparators, each receiving said first and second external clock signal, generating said first and second source clock signals.

3. The semiconductor memory device according to claim 2, further comprising a third internal clock generation circuit receiving said first source clock signal, generating a third internal clock signal synchronizing with one of said first and second external clock signals and supplying said third internal clock signal to said second interface circuit.

4. The semiconductor memory device according to claim 3, further comprising

an internal circuit performing write operations on said input data in synchronization with an operational clock,

a buffer circuit supplying said operational clock to said internal circuit, and

a switch circuit selectively providing one of said first source clock signal and said third internal clock signal to said buffer circuit.

5. The semiconductor memory device according to claim 2, wherein

said first internal clock signal has a higher frequency than the frequency of said first external clock signal,

said third interface circuit further includes a data output circuit outputting output data in synchronization with said first internal clock signal, and

the semiconductor memory device further comprises a strobe signal output circuit outputting a strobe signal in synchronization with said first internal clock signal.

6. A semiconductor memory device comprising:

a first interface circuit receiving a first external clock signal and a second external clock signal complementary to said first external clock signal from the outside of said semiconductor memory device, said first interface circuit including

a comparator generating a first source clock signal by comparing said first external clock signal with a reference voltage in a first operation mode, and generating a second source clock signal and a third source clock signal complementary to said second source clock signal by comparing said first external clock signal with said second external clock signal in a second operation mode, and

a switch circuit selectively providing one of said second external clock signal and said reference voltage to said comparator according to which one of said first and second operation modes is designated; and

an internal clock generation circuit generating an internal clock signal for data output operation based on said first source clock signal in said first operation mode, and generating said internal clock signal based on said second and third source clock signals in said second operation mode.

7. A semiconductor memory device comprising:

a first interface circuit receiving a first external clock signal and a second external clock signal complementary to said first external clock signal from the outside of said semiconductor memory device, said first interface circuit including

a comparator generating a first source clock signal by comparing said first external clock signal with a reference voltage in a first operation mode, and generating a second source clock and a third source clock signal complementary to said second source clock signal by comparing said first external clock signal with said second external clock signal in a second operation mode;

an internal clock generation circuit generating a first internal clock signal for data output operation based on said first source clock signal in said first operation mode, and generating a second internal clock signal for data output operation based on said second and third source clock signals in said second operation mode;

a second interface circuit including a data output circuit outputting output data in synchronization with said first internal clock signal in said first operation mode and in synchronization with said second internal clock signal in said second operation mode; and

a strobe signal output circuit outputting a strobe signal in synchronization with said second internal clock signal in said second operation mode.