PCM codec and modem for 56K bi-directional transmission

• US 6,522,688 B1
• Filed: 01/14/1999
• Issued: 02/18/2003
• Est. Priority Date: 01/14/1999
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Eric M. Dowling
• Inventors: Dowling, Eric Morgan
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Kim, Kevin
• Application Number:
  US09/231,183
• Time in Patent Office: 1,496 Days
• Field of Search: 375/222, 375/254, 370/352, 370/292, 370/276, 370/286, 379/442, 379/22, 379/399.01, 379/406.08
• US Class Current: 375/222
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex

Abstract

A high-speed analog subscriber modem operates at speeds as high as 64 kbps in both the downlink and uplink directions using a standard POTS line augmented with an enhanced codec. This enables increased upload speeds and supports 56 kbps peer-to-peer analog subscriber connections. An enhanced network codec according to the present invention supports on a POTS line both high-speed modem communications and standard PCM speech communication. The enhanced codec of the present invention may be designed to be plug-compatible with existing codecs and may be used to upgrade POTS service to support data rates approaching 64 kbps. Similarly, the present invention may be used to increase the use of the POTS channel in a DSL system.

Claims

1. An enhanced codec apparatus, comprising:

a digital signal processor circuit;

a digital interface port with a first coupling to said digital signal processor circuit and a second coupling to a digital network;

a digital conversion subsystem comprising a DAC wherein said DAC has a digital input coupled to receive a digitally encoded signal sample derived from said digital interface port and an analog output coupled to a first analog signal port, said digital conversion subsystem also comprising an ADC that has a digital output and an analog input;

an echo canceller processing module comprising an adaptive filter and a differential amplifier, said echo canceller processing module controllably coupled to said digital signal processing circuit and opertively coupled to receive at an X-input to said adaptive filter a digital representation of a signal derived from said digital interface port, said echo canceller processing module also operatively coupled to receive at a first input to said differential amplifier, a signal that passes through a second analog signal port, the output of said differential amplifier being coupled to said analog input of said ADC, said echo canceller processing module operative to cancel an echo component which leaks from the output of said first analog signal port back into the input of said second analog signal port when said first and second analog signal ports are coupled to a subscriber line;

a pulse decoder processing module controllably coupled to said digital signal processing circuit and having an input operatively coupled to the output of said ADC, said pulse decoder processing module operative to regenerate a PCM data stream;

wherein the output of said adaptive filter is fed through a second DAC, and a second input of said differential amplifier is coupled to the output of said second DAC.

2. The enhanced codec apparatus according to claim 1, wherein high-speed communications involves a data rate from 33.6 kbps to 56 kbps.

3. The enhanced codec apparatus according to claim 1, further comprising a chip carrier package which is pin-compatible with an existing PCM codec, whereby an existing line card can be upgraded to an enhanced line card by replacing said existing codec with said enhanced codec.

4. The enhanced codec apparatus according to claim 1, further comprising an out-of-band DSL processing circuit for processing DSL modem signals.

5. The enhanced codec according to claim 1, wherein said ADC samples its input at a first sample rate higher than a second sample rate employed by said digital interface.

6. The enhanced codec apparatus according to claim 1, further comprising:

a protocol detect processing module controllably coupled to said digital signal processing circuit, said protocol detect processing module operative to detect a transmission protocol used within said POTS portion of said subscriber line and select a pulse decoder mapping operation in response thereto.

7. The enhanced codec apparatus according to claim 6, wherein said protocol detect module is further operative to detect an echo canceller training phase in said protocol and said enhanced codec further comprises:

an echo canceller training module controllably coupled to said digital signal processing circuit and operatively coupled to receive the detection output of said protocol detect module, said echo canceller training module operative train said echo canceller when an echo canceller training phase is detected by said protocol detect processing module.

8. The enhanced codec apparatus according to claim 6, wherein said protocol detect module is further operative to detect a subscriber line equalizer training phase in said protocol and said enhanced codec further comprises:

an equalizer processing module controllably coupled to said digital signal processing circuit and operatively coupled to receive the detection output of said protocol detect module and having an output operatively coupled to the input of said pulse decoder.

9. The enhanced codec apparatus according to claim 8, wherein said ADC samples its input at a first sample rate higher than a second sample rate employed by said digital interface, and said equalizer and pulse decoder processing modules process information at said first sample rate to produce a reencoded output at said second sample rate.

10. The enhanced codec apparatus according to claim 6, further comprising:

a programmable instruction memory;

wherein said protocol detect module detects a management protocol sequence and responds thereto by loading a new program instruction into said instruction memory.

11. The enhanced codec apparatus according to claim 1, further comprising:

a first filter interposed between the analog output of said DAC and said first analog signal port; and

a second filter interposed between said second analog signal port and the analog input of said ADC.

12. The enhanced codec apparatus according to claim 1, further comprising said line interface circuit.

13. The enhanced codec apparatus according to claim 12, further comprising a line card.

14. The enhanced codec apparatus according to claim 13, further comprising a network interface equipment rack into which are plugged at least one of said line cards.

21. The enhanced codec apparatus of claim 1,

wherein the enhanced codec is for use in a network interface line card;

and

wherein said PCM data stream is coupled for transmission to said digital network via said digital interface, and said enhanced codec thereby enables high-speed digital communication in an uplink direction a using a POTS channel of a subscriber line.

15. An enhanced codes apparatus comprising:

a digital to analog converter;

an analog-to-digital converter;

a mapping function module; and

an echo canceller with an X-input coupled to the input of the digital-to-analog converter and a D-input coupled to the output of the analog-to-digital converter, said echo canceller operative to cancel an echo component leaking from the output of said digital-to-analog converter back to the input of the analog-to-digital converter;

a second digital-to-analog converter; and

a differential amplifier circuit with a first differential input coupled to a line interface circuit and a second differential input coupled to the output of said second digital-to-analog converter, the output of said differential amplifier operatively coupled to the input of said analog-to-digital converter, said differential amplifier circuit operative to cancel said echo component prior to conversion by said analog-to-digital converter;

wherein said mapping function module is operative to selectively convert a digital representation of an uplink-analog signal to one of a PCM waveform representation and a decoded bit stream inserted into a PCM data stream.

16. The apparatus of claim 15, further comprising:

a protocol detection module operative to detect whether said apparatus is being used for a high-speed uplink modem connection or a voice connection, and if said codec is used in a modem connection, to perform signal conditioning to recover a high-speed uplink bit stream, encode said high-speed uplink bit stream into a PCM data stream, and transmit said PCM data stream to a digital network.

17. The codec of claim 15, wherein said mapping function module further comprises a digital impairment compensation module.

18. The codec of claim 15, wherein said analog-to-digital converter uses a 16-bit linear format and samples at a sampling rate greater than 8000 Hz, and the mapping function module performs equalization, clock recovery, downsampling and pulse decoding to produce said PCM data stream.

19. A system for high speed voice circuit communication comprising an enhanced codec and a subscriber modem apparatus coupleable to a POTS channel of a subscriber line and operative to communicate with said enhanced codec, the apparatus comprising:

said enhanced codec comprising;

a voice band codec that processes uplink voice signals; and

a high speed uplink pulse signal demodulator, said high speed pulse signal demodulator comprising an echo canceller that cancels an uplink echo and converts a high speed pulse train received on a POTS channel to a digital output signal;

whereby said enhanced codec selectively operates as an uplink digital data conversion circuit for voice signals and an uplink data demodulator for high speed pulse modem signals; and

said subscriber modem, comprising;

a high-speed uplink transmitter coupled to transmit a high-speed pulse oriented modem signal onto the POTS channel of said subscriber line for reception by said enhanced codec, whereby said enhanced codec converts said high-speed pulse modem signal into a PCM data steam, and the combination of the enhanced codec and the subscriber modern apparatus provide substantially symmetric high speed data communication rates in an uplink and a downlink direction.

20. The subscriber modem apparatus of claim 19, further comprising:

a protocol module operative to transmit a training signal to said enhanced codec to allow said enhanced codec to configure a set of signal processing parameters contained therein.

24. The subscriber modem apparatus of claim 19, whereby the uplink data transmitter is capable of operating in a mode where it transmits pulse data to the enhanced codec to provide an uplink data rate selected between 53 kbps and 64 kbps.

22. An enhanced codec apparatus for use in a network interface line card, comprising:

a digital signal processor circuit;

a digital interface port with a first coupling to said digital signal processor circuit and a second coupling to a digital network;

a digital conversion subsystem comprising a DAC wherein said DAC has a digital input coupled to receive a digitally encoded signal sample derived from said digital interface port and an analog output coupled to a first analog signal port, said digital conversion subsystem also comprising an ADC that has a digital output and an analog input;

an echo canceller processing module comprising an adaptive filter and a differential amplifier, said echo canceller processing module controllably coupled to said digital signal processing circuit and operatively coupled to receive at an X-input to said adaptive filter a digital representation of a signal derived from said digital interface port said echo canceller processing module also operatively coupled to receive at a first input to said differential amplifier, a signal that passes through a second analog signal port, the output of said differential amplifier being coupled to said analog input of said ADC, said echo canceller processing module operative to cancel an echo component which leaks from the output of said first analog signal port back into the input of said second analog signal port when said first and second analog signal ports are coupled to a subscriber line;

a pulse decoder processing module controllably coupled to said digital signal processing circuit and having an input operatively coupled to the output of said ADC, said pulse decoder processing module operative to regenerate a PCM data stream;

wherein said PCM data stream is coupled for transmission to said digital network via said digital interface, and said enhanced code thereby enables high-speed digital communication in an uplink direction using a POTS channel of a subscriber line; and

wherein the output of said adaptive fitter is fed through a second DAC, and a second input of said differential amplifier is coupled to the output of said second DAC.

23. The enhanced codec apparatus according to claim 22, wherein said echo canceller is trained using an FXLMS algorithm.